# US 12,602,166 B2 · System-on-chip for controlling memory devices and its data training method

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- Number: US 12,602,166 B2
- Document ID: US12602166B2
- Status: Granted
- Kind: B2
- Application number: 18/890,080
- Filed: 2024-09-19
- Published: 2025-07-31
- Granted: 2026-04-14
- Earliest claimed: 2024-01-25
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Daero Kim; Boyoung Kang; Ji Hun Oh; Kyoungwon Lee; Kwanyeob Chae
- Web page: https://patentgrep.com/patent/US12602166B2

## CPC

- G06F 3/0613: {in relation to throughput}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G11C 2207/2254: Calibration
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Disclosed is a SoC. The SoC communicating with a memory device includes a memory interface that exchanges a command and data with the memory device, and a control logic circuit that transmits a clock signal and a plurality of data signals to the memory device through the memory interface. The control logic circuit sequentially transmits pieces of first data with different delay times to the memory device through the memory interface based on a pre-stored first edge code, continuously transmits, to the memory device, a plurality of read commands for reading the pieces of first data stored in the memory device from the memory device, and obtains a first delay value including an extent, to which the pieces of first data are delayed, based on a data pattern of each of pieces of first reception data read from the memory device in response to the plurality of read commands.

## Claims

### Claim 1

A system-on-Chip (SoC) communicating with a memory device, the SoC comprising:
a memory interface configured to exchange a command and data with the memory device; and
a control logic circuit configured to transmit a clock signal and a plurality of data signals to the memory device through the memory interface,
wherein the control logic circuit is configured to:
sequentially transmit a plurality of pieces of first data with a plurality of different delay times to the memory device through the memory interface based on a pre-stored first edge code;
continuously transmit, to the memory device, a plurality of read commands for reading the plurality of pieces of first data stored in the memory device from the memory device; and
obtain a first delay value based on a data pattern of each of a plurality of pieces of first reception data, wherein the first delay value includes an extent to which the plurality of pieces of first data are delayed, and wherein the plurality of pieces of first reception data are read from the memory device in response to the plurality of read commands.

### Claim 2 (depends on 1)

The SoC of claim 1, further comprising:
a code storage circuit configured to store the first edge code,
wherein the control logic circuit is configured to store a first update code obtained by reflecting the first delay value to the first edge code in the code storage circuit.

### Claim 3 (depends on 2)

The SoC of claim 2, wherein the control logic circuit is configured to control a delay of a data signal transmitted to the memory device through the memory interface based on the first update code.

### Claim 4 (depends on 1)

The SoC of claim 1, wherein the control logic circuit is configured to:
sequentially transmit a plurality of write commands to the memory device according to a specified time interval, wherein the plurality of write commands respectively correspond to the plurality of pieces of first data; and
continuously transmit the plurality of read commands to the memory device after a predetermined transition time from a point in time when the plurality of write commands are transmitted.

### Claim 5 (depends on 4)

The SoC of claim 4, wherein the control logic circuit is configured to:
sequentially write the plurality of pieces of first data in the memory device after a time corresponding to a write delay has elapsed from a point in time when a first write command among the plurality of write commands is transmitted; and
continuously read the plurality of pieces of first reception data from the memory device after a time corresponding to a read delay has elapsed from a point in time when a first read command among the plurality of read commands is transmitted.

### Claim 6 (depends on 1)

The SoC of claim 1, wherein the control logic circuit includes:
a pattern generating circuit configured to generate a first data pattern based on the first edge code; and
a delay control circuit configured to output the plurality of pieces of first data by applying the plurality of different delay times to the first data pattern.

### Claim 7 (depends on 6)

The SoC of claim 6,
wherein the memory interface includes a delay cell connected to the delay control circuit, and
wherein the delay control circuit is configured to output the plurality of pieces of first data by applying a delay corresponding to an integer multiple of a unit delay time to the first data pattern through the delay cell.

### Claim 8 (depends on 6)

The SoC of claim 6,
wherein the control logic circuit further includes a pattern checking circuit connected to the memory interface,
wherein the pattern checking circuit is configured to compare the data pattern of each piece of the plurality of pieces of first reception data read from the memory device with a data pattern of corresponding data among the plurality of pieces of first data, and
wherein the delay control circuit is configured to determine the first delay value based on the comparison result.

### Claim 9 (depends on 6)

The SoC of claim 6, wherein the pattern generating circuit is configured to generate the first data pattern based on a first generation command generated by the control logic circuit depending on a predetermined period.

### Claim 10 (depends on 6)

The SoC of claim 6, further comprising:
a detector configured to detect a characteristic variation of the memory device,
wherein when a characteristic variation value of the memory device detected through the detector exceeds a threshold value, the control logic circuit is configured to generate a first variation command,
wherein the pattern generating circuit is configured to generate first variation data pattern based on the first edge code in response to the first variation command, and
wherein the delay control circuit is configured to output pieces of variation data by applying the plurality of different delay times to the first variation data pattern.

### Claim 11 (depends on 1)

The SoC of claim 1, wherein the control logic circuit is configured to:
sequentially transmit a plurality of pieces of second data to the memory device through the memory interface based on a second edge code distinct from the first edge code, wherein another plurality of different delay times are applied to the plurality of pieces of second data;
continuously transmit a plurality of read commands for reading the pieces of second data stored in the memory device from the memory device; and
obtain a second delay value based on a data pattern of each of pieces of second reception data read from the memory device, wherein the second delay value includes an extent to which the plurality of pieces of second data are delayed.

### Claim 12

A data training method for a memory device, the method comprising:
sequentially transmitting a plurality of write commands to the memory device according to a specified time interval;
sequentially transmitting a plurality of pieces of first data with a plurality of different delay times to the memory device through a memory interface based on a pre-stored first edge code in response to each of the plurality of write commands;
continuously transmitting, to the memory device, a plurality of read commands for reading the plurality of pieces of first data stored in the memory device from the memory device; and
obtaining a first delay value based on a data pattern of pieces of first reception data read from the memory device, wherein first delay value includes an extent to which the plurality of pieces of first data are delayed.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
storing a first update code obtained by reflecting the first delay value to the first edge code in a code storage circuit; and
controlling a delay of a data signal transmitted to the memory device through the memory interface based on the first update code stored in the code storage circuit.

### Claim 14 (depends on 12)

The method of claim 12, wherein the transmitting of the plurality of pieces of first data to the memory device includes:
generating a first data pattern based on the first edge code; and
outputting the plurality of pieces of first data by applying the plurality of different delay times to the first data pattern.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
determining the first delay value by comparing the data pattern of each piece of the plurality of pieces of first reception data read from the memory device with a data pattern of each piece of the plurality of pieces of first data.

### Claim 16

A memory system comprising:
a memory device; and
a SoC configured to control a memory operation of the memory device,
wherein the SoC is configured to:
sequentially transmit a plurality of pieces of first data with a plurality of different delay times to the memory device based on a pre-stored first edge code;
continuously transmit, to the memory device, a plurality of read commands for reading the plurality of pieces of first data stored in the memory device from the memory device; and
obtain a first delay value based on a data pattern of each piece of a plurality of pieces of first reception data read from the memory device, wherein the plurality of pieces of first data are delayed in the memory device by the first delay value.

### Claim 17 (depends on 16)

The memory system of claim 16,
wherein the SoC further includes: a code storage circuit configured to store the first edge code, and
wherein the SoC is configured to store a first update code obtained by reflecting the first delay value to the first edge code in the code storage circuit.

### Claim 18 (depends on 16)

The memory system of claim 16,
wherein the first delay value includes a delay direction and a delay degree, and
wherein the SoC is configured to adjust, based on the delay direction and the delay degree, a delay of a data signal transmitted to the memory device.

### Claim 19 (depends on 16)

The memory system of claim 16, wherein the memory device includes at least one of a dynamic random access memory (DRAM), a first in first out (FIFO) memory, or a scratchpad memory.

### Claim 20 (depends on 16)

The memory system of claim 16, wherein the SoC is configured to determine the first delay value by comparing (i) the data pattern of each piece of the plurality of pieces of first reception data read from the memory device with (ii) a data pattern of corresponding data among the plurality of pieces of first data.