# US 12,602,165 B2 · Method of improving programming operations in 3D NAND systems > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,602,165 B2 - Document ID: US12602165B2 - Status: Granted - Kind: B2 - Application number: 18/824,573 - Filed: 2024-09-04 - Published: 2024-12-26 - Granted: 2026-04-14 - Earliest claimed: 2022-11-23 - Assignees: Yangtze Memory Technologies Co., Ltd. - Applicants: Yangtze Memory Technologies Co., Ltd. - Inventors: Zhe Luo; Da Li; Feng Xu; Yaoyao Tian; Jianquan Jia; Xiangnan Zhao - Web page: https://patentgrep.com/patent/US12602165B2 ## CPC - G06F 3/0613: {in relation to throughput} - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G06F 3/0629: {Configuration or reconfiguration of storage systems} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present disclosure provides a method for performing a programming operation on a memory cell connected to a bit line and controlled by a word line. The method includes applying a first programming voltage signal to the word line to program the memory cell into a first state, applying a first voltage to the bit line, performing a verify operation when the memory cell is in a second state, determining a classification of the memory cell based on the verify operation, applying a second voltage to the bit line based on the determined classification, applying a second programming voltage signal to the word line to program the memory cell into the first state, applying a third voltage to the bit line, applying a third programming voltage signal to the word line to program the memory cell into the first state, and applying a fourth voltage to the bit line. ## Claims ### Claim 1 A method of programming a memory device, the method comprising: performing a programming operation on a memory cell to program the memory cell to a first programmed state, wherein performing the programming operation comprises: applying a first program voltage to a word line coupled to the memory cell; applying a first voltage to a bit line coupled to the memory cell during application of the first program voltage; performing a pre-verify operation with a first verify voltage lower than a second verify voltage, wherein the second verify voltage corresponds to the first programmed state; and in response to the memory cell not passing the pre-verify operation, applying a second voltage to the bit line and applying a second program voltage to the word line, wherein the second voltage is lower than the first voltage and the second program voltage is higher than the first program voltage. ### Claim 2 (depends on 1) The method of claim 1, wherein the second voltage is zero. ### Claim 3 (depends on 1) The method of claim 1, wherein the first verify voltage corresponds to a second programmed state and a target voltage of the second programmed state is lower than the target voltage of the first programmed state. ### Claim 4 (depends on 1) The method of claim 1, wherein the first programmed state is the highest programmed state in the memory device. ### Claim 5 (depends on 3) The method of claim 3, wherein the second programmed state is one state lower than the first programmed state. ### Claim 6 (depends on 1) The method of claim 1, wherein performing the programming operation further comprises: in response to the memory cell passing the pre-verify operation, applying the first voltage to the bit line and applying a second program voltage to the word line. ### Claim 7 (depends on 1) The method of claim 1, wherein performing the programming operation further comprises: applying the second verify voltage to the word line after applying the first program voltage. ### Claim 8 (depends on 1) The method of claim 1, wherein performing the programming operation further comprises: performing a verify operation with a third verify voltage after applying the second program voltage, wherein the third verify voltage is lower than the second verify voltage and higher than the first verify voltage; and in response to the memory cell passing the second verify operation, applying a third voltage to the bit line and applying a third program voltage to the word line, wherein the third voltage is higher than the second voltage and the third program voltage is higher than the second program voltage. ### Claim 9 A memory device, comprising: a memory cell; a word line coupled to the memory cell; a bit line coupled to the memory cell; a peripheral circuit coupled to the word line and the bit line, and configured to: perform a programming operation on the memory cell to program the memory cell to a first programmed state, wherein performing the programming operation comprises: applying a first program voltage to the word line; applying a first voltage to the bit line during application of the first program voltage; performing a pre-verify operation with a first verify voltage lower than a second verify voltage, wherein the second verify voltage corresponds to the first programmed state; and in response to the memory cell not passing the pre-verify operation, applying a second voltage to the bit line and applying a second program voltage to the word line, wherein the second voltage is lower than the first voltage and the second program voltage is higher than the first program voltage. ### Claim 10 (depends on 9) The memory device of claim 9, wherein the second voltage is zero. ### Claim 11 (depends on 9) The memory device of claim 9, wherein the first verify voltage is corresponding to a second programmed state and a target voltage of the second programmed state is lower than the target voltage of the first programmed state. ### Claim 12 (depends on 9) The memory device of claim 9, wherein the first programmed state is the highest programmed state in the memory device. ### Claim 13 (depends on 11) The memory device of claim 11, wherein the second programmed state is one state lower than the first programmed state. ### Claim 14 (depends on 9) The memory device of claim 9, wherein perform the programming operation further comprises: in response to the memory cell passing the pre-verify operation, applying the first voltage to the bit line and applying a second program voltage to the word line. ### Claim 15 (depends on 9) The memory device of claim 9, wherein perform the programming operation further comprises: applying the second verify voltage to the word line after applying the first program voltage. ### Claim 16 (depends on 9) The memory device of claim 9, wherein perform the programming operation further comprises: performing a verify operation with a third verify voltage after applying the second program voltage, wherein the third verify voltage is lower than the second verify voltage and higher than the first verify voltage; and in response to the memory cell passing the verify operation, applying a third voltage to the bit line and applying a third program voltage to the word line, wherein the third voltage is higher than the second voltage and the third program voltage is higher than the second program voltage. ### Claim 17 A storage system, comprising: a memory controller coupled to a memory device and configured to transmit a command to the memory device; and the memory device comprising: a memory cell; a word line coupled to the memory cell; a bit line coupled to the memory cell; a peripheral circuit coupled to the word line and the bit line, and configured to: perform a programming operation on the memory cell to program the memory cell to a first programmed state, wherein performing the programming operation comprises: applying a first program voltage to the word line; applying a first voltage to the bit line during application of the first program voltage; performing a pre-verify operation with a first verify voltage lower than a second verify voltage, wherein the second verify voltage corresponds to the first programmed state; and in response to the memory cell not passing the pre-verify operation, applying a second voltage to the bit line and applying a second program voltage to the word line, wherein the second voltage is lower than the first voltage and the second program voltage is higher than the first program voltage. ### Claim 18 (depends on 17) The storage system of claim 17, wherein the second voltage is zero. ### Claim 19 (depends on 17) The storage system of claim 17, wherein the first verify voltage is corresponding to a second programmed state and a target voltage of the second programmed state is lower than the target voltage of the first programmed state. ### Claim 20 (depends on 17) The storage system of claim 17, wherein perform the programming operation further comprises: in response to the memory cell passing the pre-verify operation, applying the first voltage to the bit line and applying a second program voltage to the word line.