# US 12,602,163 B2 · Managing cross-temperature exposure in memory systems > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,602,163 B2 - Document ID: US12602163B2 - Status: Granted - Kind: B2 - Application number: 18/781,803 - Filed: 2024-07-23 - Published: 2025-09-11 - Granted: 2026-04-14 - Earliest claimed: 2024-03-06 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Gianluca Coppola - Web page: https://patentgrep.com/patent/US12602163B2 ## CPC - G06F 3/0611: {in relation to response time} - G06F 3/0653: {Monitoring storage devices or systems} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods, systems, and devices for techniques for managing cross-temperature exposure in memory systems are described. A memory system controller may identify, during a boot sequence, a temperature associated with a write operation at a logical block address (LBA) of a first memory device, where the LBA is associated with a physical address of the first memory device that stores a portion of boot sequence data. The memory system controller may select a read setting based on a difference between an operating temperature of the first memory device during the boot sequence and the temperature associated with the write operation at the LBA of the first memory device. Accordingly, the memory system controller may perform a read operation to read the portion of the boot sequence data from the physical address associated with the LBA according to the read setting. ## Claims ### Claim 1 A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: identify, during a boot sequence of the memory system, a first temperature of a first memory device of the one or more memory devices, the first temperature being obtained during a write operation at a logical block address (LBA) of the first memory device, the LBA corresponding to a physical address of the first memory device that stores a portion of boot sequence data; select a read setting from a plurality of read settings based on a difference between an operating temperature of the first memory device during the boot sequence of the memory system and the first temperature; and read the portion of the boot sequence data from the physical address corresponding to the LBA according to the read setting. ### Claim 2 (depends on 1) The memory system of claim 1, wherein, to identify the first temperature at the LBA, the processing circuitry is configured to cause the memory system to: identify the first temperature from a table comprising a plurality of LBAs and a plurality of temperatures, each of the plurality of temperatures being obtained during a respective write operation at each LBA of the plurality of LBAs. ### Claim 3 (depends on 2) The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: load the table from non-volatile memory of the memory system to volatile memory of the memory system based on a start of the boot sequence, wherein identifying the first temperature from the table is based on loading the table into the volatile memory. ### Claim 4 (depends on 2) The memory system of claim 2, wherein the processing circuitry is configured to cause the memory system to: receive, from a host system, one or more commands each indicating a LBA range at which a respective portion of the boot sequence data is stored, wherein the plurality of LBAs included in the table are based on the one or more commands. ### Claim 5 (depends on 4) The memory system of claim 4, wherein a first portion of the one or more commands comprises a starting LBA, and a second portion of the one or more commands comprises one or more LBAs from the starting LBA. ### Claim 6 (depends on 2) The memory system of claim 2, wherein the processing circuitry is configured to cause the memory system to: identify, during the respective write operation at each LBA of the plurality of LBAs, each of the plurality of temperatures; and store each of the plurality of temperatures to respective entries in the table based on identifying. ### Claim 7 (depends on 6) The memory system of claim 6, wherein the processing circuitry is configured to cause the memory system to: receive, from a host system, an indication to start a power off sequence, wherein storing each of the plurality of temperatures is based on the indication to start the power off sequence. ### Claim 8 (depends on 1) The memory system of claim 1, wherein the processing circuitry is configured to cause the memory system to: identify, during the boot sequence, the operating temperature of the first memory device, wherein selecting the read setting is based on identifying the operating temperature of the first memory device. ### Claim 9 (depends on 1) The memory system of claim 1, wherein the processing circuitry is configured to cause the memory system to: transmit the portion of the boot sequence data to a host system based on reading the portion of the boot sequence data from the physical address according to the read setting. ### Claim 10 (depends on 1) The memory system of claim 1, wherein identifying the first temperature is based on a register at the memory system being set to a first value. ### Claim 11 (depends on 10) The memory system of claim 10, wherein the processing circuitry is configured to cause the memory system to: receive, from a host system, an indication to set the register to the first value. ### Claim 12 (depends on 1) The memory system of claim 1, wherein the processing circuitry is configured to cause the memory system to: identify, during the boot sequence, a second temperature of the first memory device, the second temperature being obtained during a second write operation at a second LBA of the first memory device, the second LBA corresponding to a second physical address that stores a second portion of the boot sequence data; select a second read setting from the plurality of read settings based on a difference between the operating temperature and the second temperature; and read the second portion of the boot sequence data from the second physical address according to the second read setting. ### Claim 13 (depends on 1) The memory system of claim 1, wherein the read setting comprises a reference voltage to apply to one or more memory cells corresponding to the physical address. ### Claim 14 (depends on 1) The memory system of claim 1, wherein the plurality of read settings are stored in non-volatile memory of the memory system. ### Claim 15 A host system, comprising: one or more interfaces comprising one or more signal paths for communications with one or more memory systems; and processing circuitry coupled with the one or more interfaces and configured to cause the host system to: transmit, to a first memory system of the one or more memory systems, one or more commands each indicating a logical block address (LBA) range at which a portion of boot sequence data is stored; transmit, to the first memory system, an indication to enable a cross-temperature management procedure at the first memory system; and receive, during a boot sequence of the first memory system, the portion of the boot sequence data from the first memory system based on transmitting the indication to enable the cross-temperature management procedure. ### Claim 16 (depends on 15) The host system of claim 15, wherein, to transmit the indication to enable the cross-temperature management procedure, the processing circuitry is configured to cause the host system to: transmit an indication for the first memory system to set a register to a first value. ### Claim 17 (depends on 15) The host system of claim 15, wherein the processing circuitry is further configured to cause the host system to: transmit, to the first memory system and based on a maintenance procedure at the first memory system, one or more second commands indicating updated LBA ranges at which the boot sequence data is stored. ### Claim 18 (depends on 15) The host system of claim 15, wherein a first portion of the one or more commands comprises a starting LBA, and a second portion of the one or more commands comprises one or more LBAs from the starting LBA. ### Claim 19 A system, comprising: a memory system comprising one or more controllers and one or more memory devices coupled with the one or more controllers; and a host system coupled with the memory system and comprising one or more controllers, the one or more controllers of the host system configured to cause the host system to: transmit, to the memory system, one or more commands each indicating a respective logical block address (LBA) range at which a portion of boot sequence data is stored; and transmit, to the memory system, an indication to enable a cross-temperature management procedure at the memory system, the one or more controllers of the memory system being configured to cause the memory system to: select a read setting from a plurality of read settings based on a difference between an operating temperature of a first memory device of the one or more memory devices and a first temperature of the first memory device, the first temperature being obtained during a write operation at a LBA of the first memory device; and read the portion of the boot sequence data from a physical address corresponding to the LBA according to the read setting. ### Claim 20 (depends on 19) The system of claim 19, wherein the one or more controllers of the memory system are configured to cause the memory system to: identify, from a table comprising a plurality of LBAs and a plurality of temperatures, the first temperature, wherein each temperature of the plurality of temperatures is obtained during a respective write operation at each LBA of the plurality of LBAs, and wherein selecting the read setting is based on identifying the first temperature from the table. ### Claim 21 (depends on 19) The system of claim 19, wherein, to transmit the indication to enable the cross-temperature management procedure, the one or more controllers of the host system are configured to cause the host system to: transmit an indication for the memory system to set a register to a first value, wherein selecting the read setting is based on the register being set to the first value. ### Claim 22 (depends on 19) The system of claim 19, wherein the one or more controllers of the memory system are configured to cause the memory system to: identify, during a boot sequence of the memory system, the operating temperature of the first memory device, wherein selecting the read setting is based on identifying the operating temperature. ### Claim 23 (depends on 19) The system of claim 19, wherein a first portion of the one or more commands comprises a starting LBA, and a second portion of the one or more commands comprises one or more LBAs from the starting LBA.