# US 12,602,162 B2 · Memory training enhancements

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- Number: US 12,602,162 B2
- Document ID: US12602162B2
- Status: Granted
- Kind: B2
- Application number: 18/129,300
- Filed: 2023-03-31
- Published: 2024-10-03
- Granted: 2026-04-14
- Earliest claimed: 2023-03-31
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: Aaron D Willey
- Web page: https://patentgrep.com/patent/US12602162B2

## CPC

- G06F 3/0611: {in relation to response time}
- G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators}
- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 3/0634: {by changing the state or mode of one or more devices}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A data processing system includes a data processor having a memory controller, and a memory. The memory is coupled to the memory controller and is for reading and writing data synchronously with respect to a clock signal. The memory includes a sensor circuit that is responsive to a control signal to output a measured value without using the clock signal.

## Claims

### Claim 1

A data processing system, comprising:
a data processor having a memory controller, wherein the data processor has an output for providing a clock signal; and
an integrated circuit memory coupled to the memory controller for reading and writing data synchronously with respect to the clock signal, wherein the integrated circuit memory includes a sensor circuit that is responsive to a control signal to output a measured value without using the clock signal.

### Claim 2 (depends on 1)

The data processing system of claim 1, wherein the sensor circuit comprises:
a sensor; and
a self-timed sequencer circuit responsive to the control signal to activate the sensor, to cause the sensor to capture the measured value, and to cause the sensor to output the measured value on at least one external terminal of the integrated circuit memory.

### Claim 3 (depends on 2)

The data processing system of claim 2, wherein the sensor comprises a temperature sensor and the measured value is a temperature of the integrated circuit memory.

### Claim 4 (depends on 2)

The data processing system of claim 2, wherein the sensor comprises a voltage sensor and the measured value is a power supply voltage of the integrated circuit memory.

### Claim 5 (depends on 2)

The data processing system of claim 2, wherein the sensor comprises a frequency sensor and the measured value is representative of a frequency of the clock signal.

### Claim 6 (depends on 2)

The data processing system of claim 2, wherein the at least one external terminal of the integrated circuit memory comprises a plurality of data input/output terminals.

### Claim 7 (depends on 1)

The data processing system of claim 1, wherein:
in response to a change in an operating point of the integrated circuit memory, the data processor places the integrated circuit memory in a low power state; and
in response to initiating an exit from the low power state, the data processor:
activates the control signal, wherein the control signal is a sleep exit signal;
reads the measured value;
adjusts at least one parameter value in response to the measured value to generate at least one adjusted parameter value;
programs the at least one adjusted parameter value in one or more mode registers of the integrated circuit memory; and
returns the integrated circuit memory to a normal operation state from the low power state.

### Claim 8 (depends on 1)

The data processing system of claim 1, wherein:
the data processor adjusts at least one parameter value in response to the measured value according to a difference between the measured value and a prior measured value.

### Claim 9

An integrated circuit memory, comprising:
a control logic circuit having a first input for receiving a clock signal, a second input for receiving a command signal, and an output for providing a control signal in response to a predetermined state of the second input;
a memory array;
access circuitry responsive to commands received on the second input synchronously with the clock signal to access data in the memory array; and
a sensor circuit for outputting a measured value on at least one output terminal of the integrated circuit memory in response to an activation of the control signal,
wherein the control logic circuit is responsive to the predetermined state of the second input to activate the control signal without using the clock signal.

### Claim 10 (depends on 9)

The integrated circuit memory of claim 9, wherein the sensor circuit comprises:
a sensor; and
a self-timed sequencer circuit responsive to the control signal to activate the sensor, to cause the sensor to capture the measured value, and to cause the sensor to output the measured value on at least one external terminal of the integrated circuit memory.

### Claim 11 (depends on 10)

The integrated circuit memory of claim 10, wherein the sensor comprises a temperature sensor and the measured value is a temperature of the integrated circuit memory.

### Claim 12 (depends on 10)

The integrated circuit memory of claim 10, wherein the sensor comprises a voltage sensor and the measured value is a power supply voltage of the integrated circuit memory.

### Claim 13 (depends on 10)

The integrated circuit memory of claim 10, wherein the sensor comprises a frequency sensor and the measured value is representative of a frequency of the clock signal.

### Claim 14 (depends on 10)

The integrated circuit memory of claim 10, wherein the at least one external terminal of the integrated circuit memory comprises a plurality of data input/output terminals.

### Claim 15 (depends on 9)

The integrated circuit memory of claim 9, wherein:
the control logic circuit is responsive to a low power state entry command to place the integrated circuit memory in a low power state;
while the integrated circuit memory is in the low power state, the control logic circuit remains responsive to the predetermined state of the second input to provide the control signal without using the clock signal, wherein the control signal is a sleep exit signal; and
the control logic circuit is responsive to a low power state exit command to bring the integrated circuit memory out of the low power state.

### Claim 16 (depends on 9)

The integrated circuit memory of claim 9, further comprising:
a first set of mode registers, wherein the first set of mode registers stores a plurality of training values at a first value of a parameter;
a second set of mode registers corresponding to the first set of mode registers; and
a register including a field for storing at least one bit to indicate whether the integrated circuit memory uses the first set of mode registers or the second set of mode registers in an operation of the integrated circuit memory.

### Claim 17

A method, comprising:
determining whether a memory will enter a low power mode;
putting the memory into the low power mode comprising stopping an external clock from being provided to the memory;
detecting a wakeup event;
sensing a measured value using a sensor circuit;
adjusting a set of cold boot parameters for operating the memory according to the measured value to form current parameters; and
operating the memory using the current parameters.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
determining the set of cold boot parameters in response to a system startup; and
initially operating the memory using the cold boot parameters before determining whether the memory will enter the low power mode.

### Claim 19 (depends on 18)

The method of claim 18, wherein the adjusting comprises:
determining a difference between the measured value and a cold boot measured value corresponding to the cold boot parameters; and
adjusting said cold boot parameters based on the difference between the measured value and the cold boot measured value.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
storing the cold boot parameters in a first set of mode registers forming a first context; and
storing the current parameters in a second set of mode registers corresponding to the first set of mode registers and forming a second context,
wherein said operating comprises:
selecting the second context; and
using the current parameters to operate the memory.