# US 12,602,161 B2 · Accelerated read, modify, write operations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,602,161 B2 - Document ID: US12602161B2 - Status: Granted - Kind: B2 - Application number: 17/990,013 - Filed: 2022-11-18 - Published: 2023-06-08 - Granted: 2026-04-14 - Earliest claimed: 2021-12-03 - Assignees: Microchip Technology Incorporated - Applicants: Microchip Technology Incorporated - Inventors: Michael Catherwood; David Mickey; Ashish Desai - Web page: https://patentgrep.com/patent/US12602161B2 ## CPC - G06F 3/0611: {in relation to response time} - G06F 3/064: {Management of blocks} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0673: {Single storage device} - G06F 3/0689: {Disk arrays, e.g. RAID, JBOD} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions. The instructions, when read and executed by a processor, cause the processor to determine that a first input instruction in a code stream to be executed is to perform a read-modify-write operation, determine that the first input instruction is to target a memory location, and, based on a determination that the first input instruction is to perform the read-modify-write operation and the determination that the first input instruction is to target the memory location, convert the first input instruction to a second input instruction to target the memory location with a mask to cause an atomic operation to implement the read-modify-write operation. ## Claims ### Claim 1 An article of manufacture comprising a non-transitory machine-readable medium, the medium comprising instructions, the instructions, when read and executed by a processor, cause the processor to: determine that a first input instruction in a code stream to be executed by a processor of a microcontroller is to perform a read-modify-write operation; determine that the first input instruction is to target a memory location included in a peripheral of the processor of the microcontroller; based on determining that the first input instruction in the code stream to be executed by the processor of the microcontroller is to perform the read-modify-write operation and determining that the first input instruction is to target the memory location included in the peripheral of the processor of the microcontroller, convert the first input instruction to a second input instruction to target the memory location included in the peripheral of the processor of the microcontroller with a mask to cause an atomic operation to implement the read-modify-write operation; determine that the read-modify-write operation of the first input instruction is to be executed by the peripheral of the processor of the microcontroller; based on determining that the read-modify-write operation of the first input instruction is to be executed by the peripheral of the processor of the microcontroller, convert the first input instruction to the second input instruction to cause the read-modify-write operation to be executed by the peripheral of the processor of the microcontroller; and convert the first input instruction to the second input instruction through inclusion of a bit-specific sideband function, the bit-specific sideband function identifying an operation different from an operation of the second input instruction, to instruct the peripheral of the processor of the microcontroller to perform the read-modify-write operation on a bit of the memory location according to the mask. ### Claim 2 (depends on 1) The article of manufacture of claim 1, wherein the instructions are to cause the processor to implement the second input instruction as a MOVL instruction to move the mask and the bit-specific sideband function to the memory location. ### Claim 3 (depends on 1) The article of manufacture of claim 1, wherein the instructions are to further cause the processor to determine that the first input instruction is to target a particular bit of the memory location; and wherein, to convert the first input instruction to the second input instruction, the instructions are to further cause the processor to, based on determining that the first input instruction is to perform the read-modify-write operation and is to target the particular bit of the memory location, target the memory location with the mask, the mask to identify the particular bit of the memory location. ### Claim 4 (depends on 1) The article of manufacture of claim 1, wherein the first input instruction is a binary set, binary clear, binary toggle, AND, OR, or XOR instruction. ### Claim 5 (depends on 4) The article of manufacture of claim 4, wherein the operation identified by the bit-specific sideband function is a bit set operation, a bit clear operation, a bit toggle operation, an AND operation, an OR operation, or an XOR operation. ### Claim 6 (depends on 1) The article of manufacture of claim 1, wherein the second input instruction to target the memory location with the mask to cause the atomic operation to implement the read-modify-write operation with an operational latency of a literal value write for the processor of the microcontroller. ### Claim 7 (depends on 1) The article of manufacture of claim 1, wherein the operation identified by the bit-specific sideband function is a bit set operation, a bit clear operation, a bit toggle operation, an AND operation, an OR operation, or an XOR operation. ### Claim 8 A method, comprising: identifying a first input instruction in a code stream to be executed by a processor of a microcontroller; determining that the first input instruction is to perform a read-modify-write operation to target a memory location included in a peripheral of the processor of the microcontroller; based on determining that the first input instruction is to perform the read-modify-write operation to target the memory location included in the peripheral of the processor of the microcontroller, converting the first input instruction to a second input instruction to target the memory location included in the peripheral of the processor of the microcontroller with a mask to cause an atomic operation to implement the read-modify-write operation; and determining that the read-modify-write operation of the first input instruction is to be executed by the peripheral of the processor of the microcontroller; wherein the converting the first input instruction to the second input instruction includes, based on the determining that the read-modify-write operation of the first input instruction is to be executed by the peripheral of the processor of the microcontroller, converting the first input instruction to the second input instruction to cause the atomic operation to be executed by the peripheral of the processor of the microcontroller with the mask; wherein the converting the first input instruction to the second input instruction includes providing a bit-specific sideband function, the bit-specific sideband function identifying an operation different from an operation of the second input instruction, to instruct the peripheral to perform the read-modify-write operation on a bit according to the mask. ### Claim 9 (depends on 8) The method of claim 8, comprising implementing the second input instruction as a MOVL instruction to move the mask and the bit-specific sideband function to the memory location. ### Claim 10 (depends on 8) The method of claim 8, comprising determining that the first input instruction is to target a particular bit of the memory location; wherein the converting the first input instruction to the second input instruction includes, based on the determining that the first input instruction is to perform the read-modify-write operation and is to target the particular bit of the memory location, converting the first input instruction to the second input instruction to target the memory location with the mask, the mask to identify the particular bit of the memory location. ### Claim 11 (depends on 8) The method of claim 8, wherein the first input instruction is a binary set, binary clear, binary toggle, AND, OR, or XOR instruction. ### Claim 12 (depends on 11) The method of claim 11, wherein the operation identified by the bit-specific sideband function is a bit set operation, a bit clear operation, a bit toggle operation, an AND operation, an OR operation, or an XOR operation. ### Claim 13 (depends on 8) The method of claim 8, wherein the second input instruction to target the memory location with the mask to cause the atomic operation to implement the read-modify-write operation is executed with an operational latency of a literal value write for the processor of the microcontroller. ### Claim 14 (depends on 8) The method of claim 8, wherein the operation identified by the bit-specific sideband function is a bit set operation, a bit clear operation, a bit toggle operation, an AND operation, an OR operation, or an XOR operation. ### Claim 15 An article of manufacture comprising a non-transitory machine-readable medium, the medium comprising instructions, the instructions, when read and executed by a processor, cause the processor to execute a first input instruction, the first input instruction to perform a read-modify-write operation through use of a mask on a memory location of a peripheral of a microcontroller to cause an atomic operation to implement the read-modify-write operation; wherein: the atomic operation is to be performed by the peripheral of the microcontroller; the instructions are to cause the processor to cause performance of the atomic operation by the peripheral of the microcontroller with the mask; the instructions are to cause the processor to cause performance of the atomic operation by the peripheral of the microcontroller through issuance of a second input instruction including a bit-specific sideband function, the bit-specific sideband function identifying an operation different from an operation of the second input instruction, to instruct the peripheral of the microcontroller to perform the read-modify-write operation on a bit according to the mask. ### Claim 16 (depends on 15) The article of manufacture of claim 15, wherein the instructions are to cause the processor to cause performance of the atomic operation with a MOVL instruction to move the mask and the bit-specific sideband function to the memory location. ### Claim 17 (depends on 15) The article of manufacture of claim 15, wherein the input instruction is to target a particular bit of the memory location and the instructions are to cause the processor to target the memory location with the mask, the mask to identify the particular bit of the memory location. ### Claim 18 (depends on 15) The article of manufacture of claim 15, wherein the read-modify-write operation is a binary set, binary clear, binary toggle, AND, OR, or XOR operation. ### Claim 19 (depends on 18) The article of manufacture of claim 18, wherein the operation identified by the bit-specific sideband function is a bit set operation, a bit clear operation, a bit toggle operation, an AND operation, an OR operation, or an XOR operation. ### Claim 20 (depends on 15) The article of manufacture of claim 15, wherein instructions are to cause the processor to cause performance of the atomic operation with an operational latency of the processor of a literal value write. ### Claim 21 (depends on 15) The article of manufacture of claim 15, wherein the operation identified by the bit-specific sideband function is a bit set operation, a bit clear operation, a bit toggle operation, an AND operation, an OR operation, or an XOR operation. ### Claim 22 A method, comprising: loading a first input instruction on a processor; executing the first input instruction on the processor, the first input instruction to cause performance of a read-modify-write operation, including using a mask on a memory location of a peripheral of a microcontroller to cause an atomic operation to implement the ready-modify-write operation; causing performance of the atomic operation by the peripheral with the mask; and causing performance of the atomic operation by the peripheral with a second input instruction including a bit-specific sideband function, the bit-specific sideband function identifying an operation different from an operation of the second input instruction, to instruct the peripheral to perform the read-modify-write operation on a bit according to the mask. ### Claim 23 (depends on 22) The method of claim 22, comprising causing performance of the atomic instruction with a MOVL instruction to move the mask and the bit-specific sideband function to the memory location. ### Claim 24 (depends on 22) The method of claim 22, wherein the input instruction is to target a particular bit of the memory location and the method comprises causing performance of the atomic instruction by targeting the memory location with the mask, the mask to identify the particular bit of the memory location. ### Claim 25 (depends on 22) The method of claim 22, wherein the read-modify-write operation is a binary set, binary clear, binary toggle, AND, OR, or XOR operation. ### Claim 26 (depends on 25) The method of claim 25, wherein the operation identified by the bit-specific sideband function is a bit set operation, a bit clear operation, a bit toggle operation, an AND operation, an OR operation, or an XOR operation. ### Claim 27 (depends on 22) The method of claim 22, comprising, at the processor, causing performance of the atomic instruction with an operational latency of the processor of a literal value write. ### Claim 28 (depends on 22) The method of claim 22, wherein the operation identified by the bit-specific sideband function is a bit set operation, a bit clear operation, a bit toggle operation, an AND operation, an OR operation, or an XOR operation.