# US 12,602,159 B2 · Apparatus having segmented data lines and methods of their operation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,602,159 B2 - Document ID: US12602159B2 - Status: Granted - Kind: B2 - Application number: 18/117,553 - Filed: 2023-03-06 - Published: 2023-10-12 - Granted: 2026-04-14 - Earliest claimed: 2022-04-06 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Vikas Rana; Kalyan Chakravarthy Kavalipurapu - Web page: https://patentgrep.com/patent/US12602159B2 ## CPC - G06F 3/061: {Improving I/O performance} - G06F 3/0656: {Data buffering arrangements} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/10: Programming or data input circuits - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Memory might include an array of memory cells and a data line selectively connected to a plurality of memory cells of the array of memory cells. The data line might include a first data line segment corresponding to a first subset of memory cells of the plurality of memory cells and a second data line segment corresponding to a second subset of memory cells of the plurality of memory cells. The second data line segment is selectively connected to the first data line segment. A first page buffer might be selectively connected to the first data line segment, and a second page buffer might be selectively connected to the second data line segment. ## Claims ### Claim 1 A memory, comprising: an array of memory cells; a data line selectively connected to a plurality of memory cells of the array of memory cells, wherein the data line comprises a first data line segment corresponding to a first subset of memory cells of the plurality of memory cells and a second data line segment corresponding to a second subset of memory cells of the plurality of memory cells, and wherein the second data line segment is selectively connected to the first data line segment through a switch having a first side directly connected to the first data line segment and a second side directly connected to the second data line segment; a first page buffer selectively connected to the first data line segment on the first side of the switch; and a second page buffer selectively connected to the second data line segment on the second side of the switch. ### Claim 2 (depends on 1) The memory of claim 1, wherein the first page buffer comprises a sensing module and a data line driver module, and wherein the second page buffer comprises a sensing module. ### Claim 3 (depends on 2) The memory of claim 2, wherein the second page buffer is devoid of a data line driver module. ### Claim 4 (depends on 2) The memory of claim 2, wherein the switch is a first switch, and wherein the data line further comprises: a third data line segment corresponding to a third subset of memory cells of the plurality of memory cells; and a second switch having a first side directly connected to the second data line segment and a second side directly connected to the third data line segment; wherein the third data line segment is selectively connected to the first data line segment through the second switch, the second data line segment, and the first switch; wherein the third data line segment is selectively connected to the second data line segment through the second switch; and wherein the memory further comprises a third page buffer selectively connected to the third data line segment on the second side of the second switch. ### Claim 5 (depends on 4) The memory of claim 4, wherein the third page buffer comprises a sensing module, and wherein the third page buffer is devoid of a data line driver module. ### Claim 6 (depends on 1) The memory of claim 1, further comprising: a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to: connect the second data line segment to the first data line segment when programming a memory cell of the second subset of memory cells; and use the first page buffer to program the memory cell of the second subset of memory cells. ### Claim 7 (depends on 6) The memory of claim 6, wherein the controller is further configured to cause the memory to: isolate the second data line segment from the first data line segment when reading the memory cell of the second subset of memory cells; and use the second page buffer to read the memory cell of the second subset of memory cells. ### Claim 8 (depends on 7) The memory of claim 7, wherein the controller being configured to cause the memory to isolate the second data line segment from the first data line segment when reading the memory cell of the second subset of memory cells comprises the controller being configured to cause the memory to isolate the second data line segment from the first data line segment when reading the memory cell of the second subset of memory cells using a first type of read operation, and wherein the controller is further configured to cause the memory to: connect the second data line segment to the first data line segment when reading the memory cell of the second subset of memory cells using a second type of read operation different than the first type of read operation; and use the first page buffer to read the memory cell of the second subset of memory cells using the second type of read operation. ### Claim 9 (depends on 8) The memory of claim 8, wherein the first type of read operation is a random read operation, and wherein the second type of read operation is a sequential read operation. ### Claim 10 (depends on 1) The memory of claim 1, wherein the switch is configured to isolate the second data line segment from the first page buffer when open, and is configured to permit connection of the second data line segment to the first page buffer when closed. ### Claim 11 (depends on 10) The memory of claim 10, wherein the switch comprises a field-effect transistor. ### Claim 12 (depends on 1) The memory of claim 1, wherein the first page buffer is selectively connected to the second data line segment through the first data line segment and the switch. ### Claim 13 A memory, comprising: an array of memory cells; a data line selectively connected to a plurality of memory cells of the array of memory cells, wherein the data line comprises a first data line segment corresponding to a first subset of memory cells of the plurality of memory cells and a second data line segment corresponding to a second subset of memory cells of the plurality of memory cells, and wherein the second data line segment is selectively connected to the first data line segment through a switch; a first page buffer selectively connected to the first data line segment, and further selectively connected to the second data line segment through the first data line segment and the switch; and a second page buffer selectively connected to the second data line segment. ### Claim 14 (depends on 13) The memory of claim 13, wherein the switch comprises one or more circuit elements configured to selectively provide either an electrical connection between the first data line segment and the second data line segment, or an electrical isolation between the first data line segment and the second data line segment. ### Claim 15 (depends on 13) The memory of claim 13, wherein the switch is a first switch, and wherein the data line further comprises: a third data line segment corresponding to a third subset of memory cells of the plurality of memory cells; and a third page buffer selectively connected to the third data line segment; wherein the third data line segment is selectively connected to the second data line segment through a second switch; and wherein the first page buffer is further selectively connected to the third data line segment through the first data line segment, the first switch, the second data line segment, and the second switch. ### Claim 16 (depends on 13) The memory of claim 13, further comprising: a common source; a first transistor connected between the first page buffer and the first data line segment; a second transistor connected between the common source and the first data line segment; a third transistor connected between the second page buffer and the second data line segment; and a fourth transistor connected between the common source and the second data line segment; wherein the first transistor and the second transistor are connected in series; wherein the third transistor and the fourth transistor are connected in series; and wherein the second transistor, the first data line segment, the switch, the second data line segment, and the fourth transistor are connected in series. ### Claim 17 A memory, comprising: an array of memory cells; a data line selectively connected to a plurality of memory cells of the array of memory cells, wherein the data line comprises a first data line segment corresponding to a first subset of memory cells of the plurality of memory cells, a second data line segment corresponding to a second subset of memory cells of the plurality of memory cells, and a third data line segment corresponding to a third subset of memory cells of the plurality of memory cells; a first page buffer selectively connected to the first data line segment; a second page buffer selectively connected to the second data line segment; and a third page buffer selectively connected to the third data line segment; wherein the second data line segment is selectively connected to the first data line segment through a first switch; wherein the third data line segment is selectively connected to the second data line segment through a second switch; and wherein the first data line segment, the first switch, the second data line segment, the second switch, and the third data line segment are connected in series. ### Claim 18 (depends on 17) The memory of claim 17, wherein the first page buffer comprises a sensing module and a data line driver module, wherein the second page buffer comprises a sensing module, and wherein the third page buffer comprises a sensing module. ### Claim 19 (depends on 18) The memory of claim 18, wherein the second page buffer is devoid of a data line driver module, and wherein the third page buffer is devoid of a data line driver module. ### Claim 20 (depends on 17) The memory of claim 17, wherein the data line further comprises: a fourth data line segment corresponding to a fourth subset of memory cells of the plurality of memory cells; and a fourth page buffer selectively connected to the fourth data line segment; wherein the fourth data line segment is selectively connected to the third data line segment through a third switch; and wherein the first data line segment, the first switch, the second data line segment, the second switch, the third data line segment, the third switch, and the fourth data line segment are connected in series. ### Claim 21 (depends on 20) The memory of claim 20, wherein the first page buffer comprises a sensing module and a data line driver module, wherein the second page buffer comprises a sensing module, and wherein the third page buffer comprises a sensing module. ### Claim 22 (depends on 21) The memory of claim 21, wherein the second page buffer is devoid of a data line driver module, and wherein the third page buffer is devoid of a data line driver module.