# US 12,602,103 B2 · Abrupt shutdown and abrupt power loss management

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- Number: US 12,602,103 B2
- Document ID: US12602103B2
- Status: Granted
- Kind: B2
- Application number: 18/511,408
- Filed: 2023-11-16
- Published: 2024-05-23
- Granted: 2026-04-14
- Earliest claimed: 2022-11-17
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Marco Redaelli
- Web page: https://patentgrep.com/patent/US12602103B2

## CPC

- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 1/3212: Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/0891: using clearing, invalidating or resetting means
- G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Implementations described herein relate to abrupt shutdown and abrupt power loss management. In some implementations, a memory device may receive a reset signal and may perform an abrupt shutdown operation based on receiving the reset signal. For example, the memory device may perform a cache flush and a write protect operation. In some other implementations, the memory device may receive a reset signal and may perform an abrupt power loss operation based on receiving the reset signal. For example, the memory device may perform a write protect operation and a flash translation layer stand-by operation. The memory device may initiate a reduced power consumption state of the memory device based on a completion of the abrupt shutdown operation or the abrupt power loss operation.

## Claims

### Claim 1

A memory device, comprising:
one or more components configured to:
receive a reset signal;
perform an abrupt shutdown operation based on receiving the reset signal, wherein the one or more components, to perform the abrupt shutdown operation, are configured to:
perform a cache flush; and
perform a write protect operation based on a completion of the cache flush;
initiate a reduced power consumption state of the memory device based on a completion of the abrupt shutdown operation;
detect that a peripheral component interconnect express link between the memory device and a host device has been disconnected;
perform another write protect operation; and
initiate a flash translation layer stand-by until the peripheral component interconnect express link is re-connected and command processing has resumed.

### Claim 2 (depends on 1)

The memory device of claim 1,
wherein the one or more components are configured to abort all outstanding memory device commands prior to performing the abrupt shutdown operation.

### Claim 3 (depends on 1)

The memory device of claim 1,
wherein the abrupt shutdown operation is associated with a low battery condition of the memory device.

### Claim 4 (depends on 1)

The memory device of claim 1,
wherein the one or more components are configured to:
detect that a reference clock has stopped during a data transfer;
perform another write protect operation; and
initiate a flash translation layer stand-by until the reference clock is in a stable condition and command processing has resumed.

### Claim 5 (depends on 1)

The memory device of claim 1,
wherein the one or more components, to receive the reset signal, are configured to identify that the reset signal has transitioned from a high state to a low state.

### Claim 6 (depends on 1)

The memory device of claim 1,
wherein the one or more components, to receive the reset signal, are configured to receive the reset signal from a power management integrated circuit based on the memory device experiencing a low voltage condition.

### Claim 7 (depends on 1)

The memory device of claim 1,
wherein the memory device is an embedded multi-media card memory device or a universal flash storage memory device.

### Claim 8

An apparatus, comprising:
means for receiving a reset signal;
means for performing an abrupt shutdown operation or an abrupt power loss operation based on receiving the reset signal, wherein the means for performing the abrupt power loss operation comprise:
means for performing a write protect operation after a last memory device command has been acknowledged; and
means for performing a flash translation layer stand-by until a peripheral component interconnect express link is re-connected and command processing has resumed; and
means for initiating a reduced power consumption state of the apparatus based on a completion of the abrupt shutdown operation or the abrupt power loss operation.

### Claim 9 (depends on 8)

The apparatus of claim 8, further comprising
means for determining whether a configuration of the apparatus indicates to perform the abrupt shutdown operation or the abrupt power loss operation.

### Claim 10 (depends on 8)

The apparatus of claim 8,
wherein the means for performing the abrupt shutdown operation comprises:
means for performing a cache flush; and
means for performing a write protect operation based on a completion of the cache flush.

### Claim 11 (depends on 8)

The apparatus of claim 8, wherein the means for receiving the reset signal comprise:
means for identifying that the reset signal has transitioned from a high state to a low state.

### Claim 12 (depends on 8)

The apparatus of claim 8, wherein the means for receiving the reset signal comprise:
means for receiving the reset signal from a power management integrated circuit based on the apparatus experiencing a low voltage condition.

### Claim 13 (depends on 8)

The apparatus of claim 8, further comprising:
means for aborting all outstanding apparatus commands prior to performing the abrupt shutdown operation.

### Claim 14

A method, comprising:
receiving, by a memory device, a reset signal;
performing, by the memory device, an abrupt shutdown operation based on receiving the reset signal, wherein performing the abrupt shutdown operation comprises:
performing a cache flush; and
performing a write protect operation based on a completion of the cache flush;
initiating, by the memory device, a reduced power consumption state of the memory device based on a completion of the abrupt shutdown operation;
detecting that a peripheral component interconnect express link between the memory device and a host device has been disconnected;
performing another write protect operation; and
initiating a flash translation layer stand-by until the peripheral component interconnect express link is re-connected and command processing has resumed.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
aborting all outstanding memory device commands prior to performing the abrupt shutdown operation.

### Claim 16 (depends on 14)

The method of claim 14,
wherein the abrupt shutdown operation is associated with a low battery condition of the memory device.

### Claim 17 (depends on 14)

The method of claim 14, further comprising:
detecting that a reference clock has stopped during a data transfer;
performing another write protect operation; and
initiating a flash translation layer stand-by until the reference clock is in a stable condition and command processing has resumed.

### Claim 18 (depends on 14)

The method of claim 14,
wherein receiving the reset signal comprises:
identifying that the reset signal has transitioned from a high state to a low state.

### Claim 19 (depends on 14)

The method of claim 14,
wherein receiving the reset signal comprises:
receiving the reset signal from a power management integrated circuit based on the memory device experiencing a low voltage condition.

### Claim 20 (depends on 14)

The method of claim 14,
wherein the memory device is an embedded multi-media card memory device or a universal flash storage memory device.