Voltage reference circuit and a power management unit

A voltage reference circuit comprising:

• a first transistor comprising a gate terminal, a source terminal, and a drain terminal;
• a second transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the first transistor and the second transistor are arranged in a stacked connection between a terminal connected to ground and a terminal connected to a supply voltage, wherein a first voltage is provided at a first node between the first transistor and the second transistor;
• a first regulating transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the first regulating transistor is connected between the supply voltage and the first transistor in a stacked connection with the second transistor, wherein a second voltage is provided at a second node between the second transistor and the first regulating transistor, and wherein the first regulating transistor is connected to the first node for compensating changes in the first voltage at the first node to maintain a stable first voltage level;
• and
• a second regulating transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the second regulating transistor is connected between the supply voltage and the second transistor in a stacked connection with the first regulating transistor, wherein a third voltage is provided at a third node between the first regulating transistor and the second regulating transistor, and wherein the second regulating transistor is connected to the second node for compensating changes in the second voltage at the second node to maintain a stable second voltage level,
• wherein the voltage reference circuit is configured to output at least one of the first voltage, the second voltage, or the third voltage as a reference voltage, and
• wherein the first transistor, the second transistor, the first regulating transistor, and the second regulating transistor are all n-type metal-oxide-semiconductor, nMOS, transistors, and wherein a drain terminal of the first transistor is connected to a source terminal of the second transistor, a drain terminal of the second transistor is connected to a source terminal of the first regulating transistor and a drain terminal of the first regulating transistor is connected to a source terminal of the second regulating transistor, and wherein the first node is connected to the drain terminal of the first transistor and the source terminal of the second transistor, the second node is connected to the drain terminal of the second transistor and the source terminal of the first regulating transistor, and the third node is connected to the drain terminal of the first regulating transistor and the source terminal of the second regulating transistor.

A voltage reference circuit comprising:

• a first transistor comprising a gate terminal, a source terminal, and a drain terminal;
• a second transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the first transistor and the second transistor are arranged in a stacked connection between a terminal connected to ground and a terminal connected to a supply voltage, wherein a first voltage is provided at a first node between the first transistor and the second transistor;
• a first regulating transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the first regulating transistor is connected between the supply voltage and the first transistor in a stacked connection with the second transistor, wherein a second voltage is provided at a second node between the second transistor and the first regulating transistor, and wherein the first regulating transistor is connected to the first node for compensating changes in the first voltage at the first node to maintain a stable first voltage level;
• a second regulating transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the second regulating transistor is connected between the supply voltage and the second transistor in a stacked connection with the first regulating transistor, wherein a third voltage is provided at a third node between the first regulating transistor and the second regulating transistor, and wherein the second regulating transistor is connected to the second node for compensating changes in the second voltage at the second node to maintain a stable second voltage level;
• wherein the voltage reference circuit is configured to output at least one of the first voltage, the second voltage, or the third voltage as a reference voltage;
• and
• wherein the gate terminal of the first transistor is connected to the first node.