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US 12,601,785 B2Granted
Providing configurable security for intellectual property circuits of a processor
AssigneeIntel Corporation
InventorsRatheesh Thekke Veetil, Gauri Shankar Singh
Life of this patent
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Abstract
In one embodiment, a method includes: receiving, in a replica circuit associated with a first intellectual property (IP) circuit of a system on chip (SoC), a security policy; receiving, in the replica circuit, a test data register access message to identify an access to a first test data register of the first IP circuit; and preventing the access to the first test data register based at least in part on the security policy. Other embodiments are described and claimed.
Claims18
An apparatus comprising:
- an intellectual property (IP) circuit comprising:
- a functional circuit to perform one or more functions;
- a test access port (TAP) controller to receive and send test data;
- and
- a plurality of test data registers coupled to the TAP controller, the plurality of test data registers to store one or more test data;
- and
- a replica circuit configured to receive a security policy and gate at least a portion of a test interface based at least in part on the security policy, wherein the replica circuit comprises:
- a replica TAP controller;
- and
- a security circuit to receive the security policy and to gate access to at least one of the plurality of test data registers based at least in part on gating circuitry coupled to the security circuit;
- and
- a decode circuit coupled to the replica TAP controller, wherein the decode circuit is configured to decode an access command to identify a first test data register to be accessed, wherein the gating circuitry is configured to gate access to the first test data register based at least in part on the security policy.
9 more elements
A method comprising:
- receiving, in a replica circuit associated with a first intellectual property (IP) circuit of a system on chip (SoC), a security policy;
- receiving, in the replica circuit, a test data register access message to identify an access to a first test data register of the first IP circuit;
- and
- preventing the access to the first test data register based at least in part on the security policy, wherein the replica circuit comprises:
- a replica TAP controller;
- and
- a security circuit to receive the security policy and to gate access to at least one of a plurality of test data registers based at least in part on gating circuitry coupled to the security circuit;
- and
- a decode circuit coupled to the replica TAP controller, wherein the decode circuit is configured to decode an access command to identify a first test data register to be accessed, wherein the gating circuitry is configured to gate access to the first test data register based at least in part on the security policy.
6 more elements
A system on chip comprising:
- a first intellectual property (IP) circuit comprising:
- a first functional circuit to perform one or more functions;
- a first test access port (TAP) controller to receive and send test data;
- and
- first design for test/debug (DFX) circuitry associated with a first plurality of test data registers;
- first replica circuitry comprising a first replica TAP controller to operate in synchronization with the first TAP controller, the first replica circuitry to control access to one or more of the first plurality of test data registers in response to a security policy, wherein the first replica circuitry comprises:
- a replica TAP controller;
- and
- a security circuit to receive the security policy and to gate access to at least one of the plurality of test data registers based at least in part on the security policy gating circuitry coupled to the security circuit;
- and
- a decode circuit coupled to the replica TAP controller, wherein the decode circuit is configured to decode an access command to identify a first test data register to be accessed, wherein the gating circuitry is configured to gate access to the first test data register based at least in part on the security policy;
- and
- a security policy generator coupled to the first replica TAP circuitry, wherein the security policy generator is configured to generate the security policy.
10 more elements
Dependencies are inferred from the claim text.