Built-in self-test circuit and method for deadtime trimming
AssigneeSemiconductor Components Industries, LLC
InventorAndrea Bollati
Life of this patent
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Abstract
Illustrative test circuits and methods are provided for determining deadtime of a switched power supply (SPS) driver. The test circuit can be configured to couple a selected gate signal selected from a high side gate signal of a driver and a low side gate signal of the driver to an input of the driver via a feedback path that causes the selected gate signal to oscillate with a period indicative of propagation time delays of the driver from which a deadtime measurement can be determined. In some implementations, the test circuits and methods may be embodied as a built-in self-test module integrated into the controller chip for the SPS.
Claims25
A test circuit configured to couple a selected gate signal selected from a high side gate signal of a driver and a low side gate signal of the driver to an input of the driver via a feedback path that causes the selected gate signal to oscillate with periods indicative of propagation time delays of the driver from which a deadtime measurement can be differentially determined.
An SPS (switched power supply) controller that comprises:
- a driver configured to receive an input signal and to responsively provide a high side gate signal to a high side switching transistor and a low side gate signal to a low side switching transistor;
- and
- a test circuit configured to provide a feedback path that converts a selectable one of the high side gate signal and the low side gate signal into a sense signal and that couples a selectable one of the sense signal and an inverted sense signal to the driver as the input signal,
- the feedback path having multiple configurations, each of the multiple configurations providing the sense signal with a pulse period that indicates a corresponding one of:
- a rise time delay of the high side gate signal;
- a fall time delay of the high side gate signal;
- a rise time delay of the low side gate signal;
- and
- a fall time delay of the low side gate signal.
A test circuit that comprises:
- a comparator configured to compare a switching transistor gate signal to a threshold;
- a pulse generator coupled to the comparator and configured to provide sense signal having pulses indicating when the switching transistor gate signal exceeds the threshold;
- an inverter coupled to the pulse generator and configured to provide an inverted sense signal;
- and
- an enable gate configured to couple the inverted sense signal to a driver input when an enable signal is asserted.
A test method that comprises:
- with a comparator, comparing a switching transistor gate signal to a threshold;
- with a pulse generator, providing a sense signal having a pulse for each time the switching transistor gate signal exceeds the threshold;
- with an inverter, inverting the sense signal to provide an inverted sense signal;
- and
- with an enable gate, coupling the inverted sense signal to a driver input while an enable signal is asserted.
Dependencies are inferred from the claim text.