# US 12,601,710 B2 · Ion-sensitive field-effect transistors with local-field bias

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- Number: US 12,601,710 B2
- Document ID: US12601710B2
- Status: Granted
- Kind: B2
- Application number: 17/987,543
- Filed: 2022-11-15
- Published: 2024-05-16
- Granted: 2026-04-14
- Earliest claimed: 2022-11-15
- Assignees: GlobalFoundries U.S. Inc.
- Applicants: GlobalFoundries U.S. Inc.
- Inventors: Judson Holt; Bartlomiej Jan Pawlak; Vibhor Jain
- Web page: https://patentgrep.com/patent/US12601710B2

## CPC

- G01N 27/4148: {Integrated circuits therefor, e.g. fabricated by CMOS processing}
- G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q)

## Abstract

Structures for an ion-sensitive field-effect transistor and methods of forming same. The structure comprises a semiconductor substrate, a microfluidic channel above the semiconductor substrate, a semiconductor layer including a portion positioned as a sensing layer in the microfluidic channel, a first electrical connection coupled to the portion of the semiconductor layer, and a second electrical connection coupled to the semiconductor substrate. The portion of the semiconductor layer is spaced above the semiconductor substrate.

## Claims

### Claim 1

A structure for a sensor device, the structure comprising:
a semiconductor substrate including a top surface;
a microfluidic channel above the semiconductor substrate;
a well in the semiconductor substrate beneath the microfluidic channel, the well comprising a semiconductor material having an opposite conductivity type from the semiconductor substrate;
a semiconductor layer including a first portion positioned as a sensing layer in the microfluidic channel, the first portion of the semiconductor layer spaced above the semiconductor substrate;
a gate structure including a gate electrode and a gate dielectric layer that are positioned on the top surface of the semiconductor substrate, the gate structure extending transversely across the first portion of the semiconductor layer;
an electrode positioned over the first portion of the semiconductor layer;
a first dielectric layer;
a first electrical connection coupled to the first portion of the semiconductor layer; and
a second electrical connection including a contact in the first dielectric layer at a periphery of the microfluidic channel, the contact physically and electrically coupled to the semiconductor substrate,
wherein the contact is included in the second electrical connection for applying a bias voltage between the semiconductor substrate and the electrode.

### Claim 2 (depends on 1)

The structure of claim 1 further comprising:
a first doped region in the semiconductor substrate beneath the microfluidic channel, the first doped region having a first conductivity type; and
a second doped region in the semiconductor substrate beneath the microfluidic channel, the first doped region having a second conductivity type opposite to the first conductivity type.

### Claim 3 (depends on 2)

The structure of claim 2 wherein the gate structure is positioned in a lateral direction between the first doped region and the second doped region.

### Claim 4 (depends on 2)

The structure of claim 2 wherein the first portion of the semiconductor layer is positioned in a lateral direction between the first doped region and the second doped region.

### Claim 5 (depends on 1)

The structure of claim 1 further comprising:
a layer stack including the first portion of the semiconductor layer and a second dielectric layer positioned between the first portion of the semiconductor layer and the semiconductor substrate.

### Claim 6 (depends on 5)

The structure of claim 5 wherein the second dielectric layer is a buried oxide layer of a silicon-on-insulator substrate.

### Claim 7 (depends on 1)

The structure of claim 1 wherein the first portion of the semiconductor layer is suspended above the semiconductor substrate to define a gap between the first portion of the semiconductor layer and the semiconductor substrate.

### Claim 8 (depends on 1)

The structure of claim 1 wherein the semiconductor layer includes a second portion and a third portion, and the first portion is longitudinally arranged between the second portion and the third portion.

### Claim 9 (depends on 8)

The structure of claim 8 wherein the first electrical connection comprises the second portion of the semiconductor layer.

### Claim 10 (depends on 8)

The structure of claim 8 further comprising:
a second dielectric layer positioned between the second portion and the third portion of the semiconductor layer and the semiconductor substrate.

### Claim 11 (depends on 10)

The structure of claim 10 wherein the second dielectric layer is positioned between the first portion of the semiconductor layer and the semiconductor substrate.

### Claim 12 (depends on 10)

The structure of claim 10 wherein the first portion of the semiconductor layer is suspended above the semiconductor substrate to define a gap between the first portion of the semiconductor layer and the semiconductor substrate.

### Claim 13 (depends on 8)

The structure of claim 8 wherein the first portion of the semiconductor layer is a strip of semiconductor material extending longitudinally from the second portion of the semiconductor layer to the third portion of the semiconductor layer.

### Claim 14

A method of forming a structure for a sensor device, the method comprising:
forming a microfluidic channel above a semiconductor substrate;
forming a well in the semiconductor substrate beneath the microfluidic channel, wherein the well comprises a semiconductor material having an opposite conductivity type from the semiconductor substrate;
forming a portion of a semiconductor layer positioned as a sensing layer in the microfluidic channel, wherein the portion of the semiconductor layer is spaced above the semiconductor substrate;
forming a gate structure including a gate electrode and a gate dielectric layer that are positioned on a top surface of the semiconductor substrate, wherein the gate structure extends transversely across the portion of the semiconductor layer;
forming an electrode positioned over the portion of the semiconductor layer;
forming a dielectric layer;
forming a first electrical connection coupled to the portion of the semiconductor layer; and
forming a second electrical connection including a contact in the dielectric layer at a periphery of the microfluidic channel, wherein the contact is physically and electrically coupled to the semiconductor substrate, and the contact is included in the second electrical connection for applying a bias voltage between the semiconductor substrate and the electrode.

### Claim 15 (depends on 1)

The structure of claim 1 wherein the semiconductor layer comprises single-crystal silicon.