# US 12,601,709 B2 · Semiconductor device with sensor and manufacturing method thereof

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- Number: US 12,601,709 B2
- Document ID: US12601709B2
- Status: Granted
- Kind: B2
- Application number: 17/830,359
- Filed: 2022-06-02
- Published: 2023-12-07
- Granted: 2026-04-14
- Earliest claimed: 2022-06-02
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Wei Lee; Chung-Liang Cheng; Pei-Wen Liu; Ke-Wei Su; Kuan-Lun Cheng
- Web page: https://patentgrep.com/patent/US12601709B2

## CPC

- G01N 27/4148: {Integrated circuits therefor, e.g. fabricated by CMOS processing}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 88/00: Three-dimensional [3D] integrated devices
- G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a substrate, an interconnect, and a sensor. The substrate includes devices therein and has a front side and a rear side opposite to the front side. The interconnect is disposed on the front side and electrically coupled to the devices. The sensor is disposed over the substrate and in the interconnect, and includes a sensing element and a reference element. The sensing element is disposed in a topmost layer of the interconnect and exposed therefrom, where the sensing element is electrically coupled to a first device of the devices through the interconnect. The reference element is disposed in the topmost layer of the interconnect and exposed therefrom, where the reference element is laterally spaced from the sensing element and is electrically coupled to a second device of the devices through the interconnect.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate, comprising devices therein, and having a front side and a rear side opposite to the front side;
an interconnect, disposed on the front side and electrically coupled to the devices; and
a sensor, disposed over the substrate and in the interconnect, comprising:
a sensing element, disposed in a topmost layer of the interconnect and exposed therefrom, wherein the sensing element is electrically coupled to a first device of the devices, and comprising:
a first gate electrode;
a first semiconductor layer, disposed over the first gate electrode;
a pair of first source/drain regions, vertically disposed over the first semiconductor layer; and
a first sensing layer, disposed on the first semiconductor layer and over the first gate electrode; and
a reference element, disposed in the topmost layer of the interconnect and exposed therefrom, wherein the reference element is laterally spaced from the sensing element and is electrically coupled to a second device of the devices, and comprising:
a second gate electrode;
a second semiconductor layer, disposed over the second gate electrode;
a pair of second source/drain regions, vertically disposed over the second semiconductor layer; and
a second sensing layer, disposed on the second semiconductor layer and over the second gate electrode.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein
the sensing element further comprises:
a first gate structure, comprising the first gate electrode and a first gate dielectric layer disposed thereon,
wherein the pair of first source/drain regions stand on the first semiconductor layer, and the first semiconductor layer is vertically between the first gate structure and the pair of first source/drain regions, and,
the reference element further comprises:
a second gate structure, comprising the second gate electrode and a second gate dielectric layer disposed thereon,
wherein the pair of second source/drain regions stand on the second semiconductor layer, and the second semiconductor layer is vertically between the second gate structure and the pair of second source/drain regions.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the sensor further comprises at least one additional sensing element, and the at least one additional sensing element comprises:
a third gate structure, comprising a third gate electrode and a third gate dielectric layer disposed thereon;
a third semiconductor layer, disposed on the third gate structure and over the third gate electrode;
a pair of third source/drain regions, standing on the third semiconductor layer, wherein the third semiconductor layer is between the third gate structure and the pair of third source/drain regions; and
a third sensing layer, disposed on the third semiconductor layer and over the third gate electrode.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein
the sensing element further comprises:
a first gate structure, comprising the first gate electrode and a first gate dielectric layer disposed thereon,
wherein the pair of first source/drain regions stand underneath the first semiconductor layer and laterally next to and spacing apart from the first gate structure, and
the reference element further comprises:
a second gate structure, comprising the second gate electrode and a second gate dielectric layer disposed thereon,
wherein the pair of second source/drain regions stand underneath the second semiconductor layer and laterally next to and spacing apart from the second gate structure.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the sensor further comprises at least one additional sensing element, and the at least one additional sensing element comprises:
a third gate structure, comprising a third gate electrode and a third gate dielectric layer disposed thereon;
a pair of third source/drain regions, disposed next to and spacing apart from the third gate structure;
a third semiconductor layer, disposed on the third gate structure and the pair of third source/drain regions, wherein the third semiconductor layer extends from one of the pair of third source/drain regions to other one of the pair of third source/drain regions, and
a third sensing layer, disposed on the third semiconductor layer and over the third gate electrode.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the sensing element is laterally separated from the reference element by a distance approximately ranging from 10 nm to 1000 nm.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the sensing element comprising a plurality of sensing elements, and the reference element and the plurality of sensing element are arranged in form of an array.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein:
the sensing element is enclosed inside an inner sidewall of the reference element, or
the reference element is enclosed inside an inner sidewall of the sensing element.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, further comprising a cap disposed on the interconnect, wherein a cavity configurated to accommodate a fluid having a to-be-tested target is formed between the cap and the interconnect, and the sensor is exposed to the cavity.

### Claim 10

A method of manufacturing a semiconductor device, comprising:
providing a substrate comprising devices therein, the substrate having a front side and a rear side opposite to the front side;
disposing an interconnect on the front side and electrically coupling the interconnect to the devices; and
forming a sensor over the substrate and in the interconnect, the sensor comprising a sensing element and a reference element disposed in a topmost layer of the interconnect and exposed therefrom, wherein the sensing element is electrically coupled to a first device of the devices and comprises a first gate electrode, a first semiconductor layer disposed over the first gate electrode, a pair of first source/drain regions vertically disposed over the first semiconductor layer, and a first sensing layer disposed on the first semiconductor layer and over the first gate electrode, and wherein the reference element is laterally spaced from the sensing element and electrically coupled to a second device of the devices, and the reference element comprises a second gate electrode, a second semiconductor layer disposed over the second gate electrode, a pair of second source/drain regions vertically disposed over the second semiconductor layer, and a second sensing layer disposed on the second semiconductor layer and over the second gate electrode.

### Claim 11 (depends on 10)

The method of claim 10, wherein forming the sensing comprises:
forming the sensing element, comprising:
providing a first gate structure comprising the first gate electrode and a first gate dielectric layer disposed thereon;
disposing the first semiconductor layer on the first gate structure and over the first gate electrode;
forming the pair of first source/drain regions standing on the first semiconductor layer, the first semiconductor layer being between the first gate structure and the pair of first source/drain regions; and
disposing the first sensing layer on the first semiconductor layer and over the first gate electrode; and
forming the reference element, comprising:
providing a second gate structure comprising the second gate electrode and a second gate dielectric layer disposed thereon;
disposing the second semiconductor layer on the second gate structure and over the second gate electrode;
forming the pair of second source/drain regions standing on the second semiconductor layer, the second semiconductor layer being between the second gate structure and the pair of second source/drain regions; and
disposing the second sensing layer on the second semiconductor layer and over the second gate electrode.

### Claim 12 (depends on 11)

The method of claim 11, wherein:
forming the sensing element further comprises:
disposing a first passivation layer over the first semiconductor layer prior to disposing the first sensing layer and after forming the pair of first source/drain regions, the first passivation layer comprising a first opening exposing the first semiconductor layer,
wherein the first sensing layer extends into the first opening to be in contact with the first semiconductor layer, and
forming the reference element further comprises:
disposing a second passivation layer over the second semiconductor layer prior to disposing the second sensing layer and after forming the pair of second source/drain regions, the second passivation layer comprising a second opening exposing the second semiconductor layer,
wherein the second sensing layer extends into the second opening to be in contact with the second semiconductor layer.

### Claim 13 (depends on 10)

The method of claim 10, wherein forming the sensing comprising:
forming the sensing element, comprising:
providing a first gate structure comprising the first gate electrode and a first gate dielectric layer disposed thereon;
forming the pair of first source/drain regions next to and spacing apart from the first gate structure;
disposing the first semiconductor layer on the first gate structure and the pair of first source/drain regions, the first semiconductor layer extending from one of the pair of first source/drain regions to other one of the pair of first source/drain regions; and
disposing the first sensing layer on the first semiconductor layer and over the first gate electrode; and
forming the reference element, comprising:
providing a second gate structure comprising the second gate electrode and a second gate dielectric layer disposed thereon;
forming the pair of second source/drain regions next to and spacing apart from the second gate structure;
disposing the second semiconductor layer on the second gate structure and the pair of second source/drain regions, the second semiconductor layer extending from one of the pair of second source/drain regions to other one of the pair of second source/drain regions; and
disposing the second sensing layer on the second semiconductor layer and over the second gate electrode.

### Claim 14 (depends on 10)

The method of claim 10, further comprising:
disposing a cap on the interconnect to form a cavity between the cap and the interconnect, wherein the cavity is configurated to accommodate a fluid having a to-be-tested target, and the sensor is exposed to the cavity.

### Claim 15 (depends on 1)

The semiconductor device of claim 1, wherein the sensing element comprising a plurality of sensing elements, and the reference element and the plurality of sensing element are arranged in form of a line, in a plane view.

### Claim 16 (depends on 1)

The semiconductor device of claim 1, wherein the sensing element comprising a plurality of sensing elements, and the plurality of sensing element are arranged at two opposite edges of the reference element, in a plane view.

### Claim 17 (depends on 1)

The semiconductor device of claim 1, wherein the sensing element comprising a plurality of sensing elements, and the plurality of sensing element are arranged at two or more edges of the reference element, in a plane view.

### Claim 18 (depends on 1)

The semiconductor device of claim 1, wherein the sensing element surrounds the reference element, in a plane view.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein a shape of the sensing element comprises a rectangular frame shape or a circular frame shape, in the plane view.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, wherein a shape of the reference element comprises a rectangular shape or a circular shape, in the plane view.