# US 12,600,239 B2 · Drive apparatus and electric vehicle

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- Number: US 12,600,239 B2
- Document ID: US12600239B2
- Status: Granted
- Kind: B2
- Application number: 18/304,597
- Filed: 2023-04-21
- Published: 2023-11-02
- Granted: 2026-04-14
- Earliest claimed: 2022-04-29
- Assignees: Huawei Digital Power Technologies Co., Ltd.
- Applicants: Huawei Digital Power Technologies Co., Ltd.
- Inventors: Xuejuan Kong; Yang Zhao; Xin Wu; Yankun Xu
- Web page: https://patentgrep.com/patent/US12600239B2

## CPC

- B60L 3/0061: {relating to electrical machines}
- B60L 3/0084: {relating to control modules}
- B60W 10/08: including control of electric propulsion units, e.g. motors or generators
- G06F 1/24: Resetting means
- G06F 11/0757: {by exceeding a time limit, i.e. time-out, e.g. watchdogs}
- B60L 3/003: {relating to inverters}
- B60L 3/0092: {with use of redundant elements for safety purposes}
- B60L 2220/42: with use of more than one motor
- Y02T 10/72: Electric energy management in electromobility
- B60L: PROPULSION OF ELECTRICALLY-PROPELLED VEHICLES (arrangements or mounting of electrical propulsion units or of plural diverse prime-movers for mutual or common propulsion in vehicles B60K1/00, B60K6/20; arrangements or mounting of electrical gearing in vehicles B60K17/12, B60K17/14; preventing wheel slip by reducing power in rail vehicles B61C15/08; dynamo-electric machines H02K; control or regulation of electric motors H02P); SUPPLYING ELECTRIC POWER FOR AUXILIARY EQUIPMENT OF ELECTRICALLY-PROPELLED VEHICLES (electric coupling devices combined with mechanical couplings of vehicles B60D1/64; electric heating for vehicles B60H1/00); ELECTRODYNAMIC BRAKE SYSTEMS FOR VEHICLES IN GENERAL (control or regulation of electric motors H02P); MAGNETIC SUSPENSION OR LEVITATION FOR VEHICLES; MONITORING OPERATING VARIABLES OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRIC SAFETY DEVICES FOR ELECTRICALLY-PROPELLED VEHICLES
- B60W: CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE OR DIFFERENT FUNCTION; CONTROL SYSTEMS SPECIALLY ADAPTED FOR HYBRID VEHICLES; ROAD VEHICLE DRIVE CONTROL SYSTEMS FOR PURPOSES NOT RELATED TO THE CONTROL OF A PARTICULAR SUB-UNIT
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02T: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION

## Abstract

A drive apparatus and an electric vehicle are provided to implement fault monitoring functions of two control chips when one watchdog chip is configured. The drive apparatus includes a first control chip, a second control chip, a first drive circuit, a second drive circuit, a watchdog chip, and a reset shutdown circuit. The first drive circuit generates a drive signal of a first inverter. The second drive circuit generates a drive signal of a second inverter. The first control chip and the second control chip perform fault monitoring on each other.

## Claims

### Claim 1

A drive apparatus, used in an electric vehicle, wherein the electric vehicle comprises a first motor, a second motor, a first inverter configured to supply power to the first motor, a second inverter configured to supply power to the second motor, and the drive apparatus, and the drive apparatus comprises a first control chip, a second control chip, a first drive circuit, a second drive circuit, a watchdog chip, and a reset shutdown circuit;
the first drive circuit is configured to generate a drive signal of the first inverter based on signals output by the first control chip and the reset shutdown circuit;
the second drive circuit is configured to generate a drive signal of the second inverter based on signals output by the second control chip and the reset shutdown circuit;
the first control chip is configured to:
send a first watchdog feeding signal to the second control chip,
receive a second watchdog feeding signal sent by the second control chip,
perform fault monitoring on the second control chip based on the second watchdog feeding signal, and
when the second control chip is faulty, control the reset shutdown circuit to send a first shutdown signal to the second drive circuit and to send a first reset signal to the second control chip, wherein the first shutdown signal is used to shut down drive torque output by the second motor, and the first reset signal is used to reset the second control chip;
the second control chip is configured to:
receive the first watchdog feeding signal, send the second watchdog feeding signal to the first control chip,
perform fault monitoring on the first control chip based on the first watchdog feeding signal, and
when the first control chip is faulty, control the reset shutdown circuit to send a second shutdown signal to the first drive circuit and to send a second reset signal to the first control chip, wherein the second shutdown signal is used to shut down drive torque output by the first motor, and the second reset signal is used to reset the first control chip; and
the watchdog chip is configured to supply power to the first control chip, the second control chip, and the reset shutdown circuit.

### Claim 2 (depends on 1)

The drive apparatus according to claim 1, wherein the first control chip is further configured to output a third watchdog feeding signal to the watchdog chip when determining that the second control chip is faulty; and
the watchdog chip is further configured to:
receive the third watchdog feeding signal, perform fault monitoring on the first control chip based on the third watchdog feeding signal, and
when determining that the first control chip is faulty, control the reset shutdown circuit to send the second reset signal to the first control chip and to send the second shutdown signal to the first drive circuit.

### Claim 3 (depends on 1)

The drive apparatus according to claim 1, wherein the second control chip is further configured to output a fourth watchdog feeding signal to the watchdog chip when determining that the first control chip is faulty; and
the watchdog chip is further configured to:
receive the fourth watchdog feeding signal,
perform fault monitoring on the second control chip based on the fourth watchdog feeding signal, and
when determining that the second control chip is faulty, control the reset shutdown circuit to send the first reset signal to the second control chip and to send the first shutdown signal to the second drive circuit.

### Claim 4 (depends on 3)

The drive apparatus according to claim 3, wherein the first control chip is further configured to send a first safety exception signal to the reset shutdown circuit, and the first safety exception signal represents that a hardware circuit of the first control chip works abnormally;
the second control chip is further configured to send a second safety exception signal to the reset shutdown circuit, and the second safety exception signal represents that a hardware circuit of the second control chip works abnormally; and
the reset shutdown circuit is further configured to:
send the second shutdown signal to the first drive circuit when receiving the first safety exception signal, and
send the first shutdown signal to the second drive circuit when receiving the second safety exception signal.

### Claim 5 (depends on 4)

The drive apparatus according to claim 4, further comprising:
a first sampling circuit configured to sample a running parameter of the first motor and output the running parameter to the first control chip; and
a second sampling circuit is configured to sample a running parameter of the second motor and output the running parameter to the second control chip, wherein
the watchdog chip is further configured to supply power to the first sampling circuit and the second sampling circuit.

### Claim 6 (depends on 4)

The drive apparatus according to claim 4, wherein the reset shutdown circuit comprises:
a first OR gate circuit, a second OR gate circuit, a third OR gate circuit, and a fourth OR gate circuit;
a first input terminal of the first OR gate circuit is connected to the first control chip, a second input terminal of the first OR gate circuit is connected to the second control chip, and an output terminal of the first OR gate circuit is connected to the first drive circuit;
a first input terminal of the second OR gate circuit is connected to the second control chip, a second input terminal of the second OR gate circuit is connected to the first control chip, and an output terminal of the second OR gate circuit is connected to the second drive circuit;
a first input terminal of the third OR gate circuit is connected to the second control chip, and an output terminal of the third OR gate circuit is connected to a reset terminal of the first control chip; and
a first input terminal of the fourth OR gate circuit is connected to the first control chip, and an output terminal of the fourth OR gate circuit is connected to a reset terminal of the second control chip.

### Claim 7 (depends on 6)

The drive apparatus according to claim 6, wherein both a third input terminal of the first OR gate circuit and a third input terminal of the second OR gate circuit are connected to the watchdog chip; and
both a second input terminal of the third OR gate circuit and a second input terminal of the fourth OR gate circuit are connected to the watchdog chip.

### Claim 8 (depends on 4)

The drive apparatus according to claim 4, wherein the reset shutdown circuit comprises: a first AND gate circuit, a second AND gate circuit, a third AND gate circuit, a fourth AND gate circuit, a fifth AND gate circuit, a sixth AND gate circuit, a seventh AND gate circuit, an eighth AND gate circuit, a first inverter, and a second inverter;
a first input terminal of the first AND gate circuit is connected to the first control chip, a second input terminal of the first AND gate circuit is connected to the first control chip, and an output terminal of the first AND gate circuit is connected to an input terminal of the first inverter;
a first input terminal of the second AND gate circuit is connected to the watchdog chip, a second input terminal of the second AND gate circuit is connected to an output terminal of the second inverter, and an output terminal of the second AND gate circuit is connected to a reset terminal of the first control chip;
a first input terminal of the third AND gate circuit is connected to the first control chip, a second input terminal of the third AND gate circuit is connected to the output terminal of the second inverter, and an output terminal of the third AND gate circuit is connected to a first input terminal of the fourth AND gate circuit;
a second input terminal of the fourth AND gate circuit is connected to the watchdog chip, and an output terminal of the fourth AND gate circuit is connected to the first drive circuit;
a first input terminal of the fifth AND gate circuit is connected to the second control chip, a second input terminal of the fifth AND gate circuit is connected to the second control chip, and an output terminal of the fifth AND gate circuit is connected to an input terminal of the second inverter;
a first input terminal of the sixth AND gate circuit is connected to the watchdog chip, a second input terminal of the sixth AND gate circuit is connected to an output terminal of the first inverter, and an output terminal of the sixth AND gate circuit is connected to a reset terminal of the second control chip;
a first input terminal of the seventh AND gate circuit is connected to the second control chip, a second input terminal of the seventh AND gate circuit is connected to the output terminal of the first inverter, and an output terminal of the seventh AND gate circuit is connected to a first input terminal of the eighth AND gate circuit; and
a second input terminal of the eighth AND gate circuit is connected to the watchdog chip, and an output terminal of the eighth AND gate circuit is connected to the second drive circuit.