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US 12,599,050 B2Granted
Multi-level die coupled with a substrate
AssigneeIntel Corporation
InventorsOmkar Karhade, Sai Vadlamani, Xavier F. Brun, Hemanth Dhavaleswarapu
Life of this patent
Estimating the term…
Abstract
Embodiments described herein may be related to apparatuses, processes, and techniques related to multilevel dies, in particular to photonics integrated circuit dies with a thick portion and a thin portion, where the thick portion is placed within a cavity in a substrate and the thin portion serves as an overhang to physically couple with the substrate, to reduce a distance between electrical contacts on the thin portion of the die and electrical contacts on the substrate. Other embodiments may be described and/or claimed.
Claims21
An apparatus, comprising:
- a single integrated circuit die having a first side and a second side opposite the first side, the second side having a first level and a second level, wherein the first level of the second side is at a first distance with respect to the first side, and the second level of the second side is at a second distance from the first side, wherein the first distance is less than the second distance;
- and
- one or more electrical connections on the first side of the single integrated circuit die, the one or more electrical connections vertically overlapping with the first level of the second side of the single integrated circuit die.
A method comprising:
- forming a single integrated circuit die having a first side and a second side opposite the first side, the second side having a first level and a second level, wherein the first level of the second side is at a first distance respect to the first side, and the second level of the second side is at a second distance from the first side, wherein the first distance is less than the second distance;
- and
- coupling one or more electrical connections on the first side of the single integrated circuit die above the first level of the second side of the single integrated circuit die, the one or more electrical connections vertically overlapping with the first level of the second side of the single integrated circuit die.
A package comprising:
- a single integrated circuit die having a first side and a second side opposite the first side, the second side having a first level and a second level, wherein the first level of the second side is at a first distance with respect to the first side, and the second level of the second side is at a second distance from the first side, wherein the first distance is less than the second distance, and wherein one or more electrical connections are on the first side of the single integrated circuit die, the one or more electrical connections vertically overlapping with the first level of the second side of the single integrated circuit die;
- a substrate that has a first side and a second side opposite the first side, the first side of the substrate having a first level and a second level, wherein the first level of the first side of the substrate is at a first distance with respect to the second side of the substrate, and the second level of the first side of the substrate is at a second distance with respect to the second side of the substrate, wherein the first distance is greater than the second distance;
- wherein the first level of the second side of the single integrated circuit die is physically coupled with the first level of the first side of the substrate, and
- wherein the second level of the second side of the single integrated circuit die is physically coupled with the second-level of the first side of the substrate.
1 more element
An apparatus, comprising:
- a die having a first side and a second side opposite the first side, the second side having a first level and a second level, wherein the first level of the second side is at a first distance with respect to the first side, and the second level of the second side is at a second distance from the first side, wherein the first distance is less than the second distance, wherein the die includes a photonics integrated circuit (PIC);
- and
- one or more electrical connections on the first side of the die.
Dependencies are inferred from the claim text.