Three-dimensional integrated circuit structure and a method of fabricating the same

An integrated circuit structure, comprising:

• a first die including a first power delivery network, a first substrate, a first device layer, and a first metal layer that are sequentially stacked;
• a second die on the first die, the second die including a second power delivery network, a second substrate, a second device layer, and a second metal layer that are sequentially stacked:
• a through electrode that extends from the first power delivery network to a top surface of the first metal layer;
• and
• a through contact that extends from the second power delivery network to the second metal layer, is horizontally offset relative to the through electrode,
• wherein the through contact penetrates the second power delivery network,
• wherein the through electrode electrically connects the first power delivery network to the second power delivery network,
• wherein the through contact electrically connects the first metal layer to the second metal layer,
• wherein a diameter of a lower portion of the through electrode is greater than a diameter of an upper portion of the through electrode,
• wherein a diameter of a lower portion of the through contact is greater than a diameter of an upper portion of the through contact, and
• wherein the through contact extends to a bottom surface of the second power delivery network.

An integrated circuit structure, comprising:

• a first power delivery network that includes a plurality of stacked first lower lines;
• a first semiconductor substrate on the first power delivery network;
• a first device layer that includes a plurality of first transistors on the first semiconductor substrate;
• a first metal layer that includes a plurality of first wiring lines stacked on the first device layer;
• a first through via that electrically connects the first power delivery network to the first device layer;
• a through electrode that extends from the first power delivery network to a top surface of the first metal layer;
• a second power delivery network on the first metal layer, the second power delivery network including a plurality of stacked second lower lines;
• a second semiconductor substrate on the second power delivery network;
• a second device layer that includes a plurality of second transistors on the second semiconductor substrate;
• a second metal layer that includes a plurality of second wiring lines stacked on the second device layer;
• a through contact that extends from the second power delivery network to the second metal layer, is horizontally offset relative to the through electrode and is able to transfer power;
• and
• a second through via that electrically connects the second power delivery network to the second device layer,
• wherein the through contact penetrates the second power delivery network and extends to a bottom surface of the second power delivery network,
• wherein the second power delivery network is electrically connected to the through electrode,
• wherein a power applied to the first power delivery network is transferred via the through electrode to the second power delivery network,
• wherein the first power delivery network is configured to transfer the power to the first device layer, and
• wherein the second power delivery network is configured to transfer the power to the second device layer.