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US 12,599,037 B2Granted
Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsSong-Soo Kim, Taeduk Nam
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes first semiconductor chips stacked on a package substrate, a lowermost first semiconductor chip of the first semiconductor chips including a recessed region, and a second semiconductor chip inserted in the recessed region, the second semiconductor chip being connected to the package substrate.
Claims20
A semiconductor package, comprising:
- a first set of semiconductor chips stacked on a package substrate and including a lowermost semiconductor chip and a plurality of semiconductor chips stacked on the lowermost semiconductor chip, the lowermost semiconductor chip of the first set of semiconductor chips including a first protruding portion protruding horizontally in a horizontal direction parallel to a top surface of the package substrate to overhang above the package substrate;
- a second set of semiconductor chips stacked on the package substrate and including a lowermost semiconductor chip and a plurality of semiconductor chips stacked on the lowermost semiconductor chip, the lowermost semiconductor chip of the second set of semiconductor chips including a second protruding portion protruding horizontally in a direction parallel to the top surface of the package substrate to overhang the package substrate, such that the first protruding portion faces the second protruding portion with a gap therebetween;
- and
- an additional semiconductor chip disposed below the first protruding portion and the second protruding portion to overlap each of the first protruding portion and the second protruding portion in a vertical direction perpendicular to the horizontal direction, the additional semiconductor chip being electrically connected to the package substrate,
- wherein the additional semiconductor chip is disposed between the first protruding portion and the package substrate and between the second protruding portion and the package substrate.
2 more elements
A semiconductor package, comprising:
- a package substrate;
- a first semiconductor chip on a center region of the package substrate, the first semiconductor chip being electrically connected to the package substrate, and the first semiconductor chip having a first side surface and a second side surface, which are opposite to each other in a horizontal direction;
- and
- second to fifth semiconductor chips, each overlapping the first side surface of the first semiconductor chip, the second to fifth semiconductor chips being sequentially stacked on the first semiconductor chip in the vertical direction, and the second to fifth semiconductor chips being electrically connected to the package substrate,
- wherein the second semiconductor chip includes a first semiconductor substrate and a first circuit layer on the first semiconductor substrate,
- wherein the first semiconductor substrate includes a first recessed region, in which the first semiconductor chip is inserted, so that part of the first semiconductor chip is between the second semiconductor chip and the package substrate to be covered by the second semiconductor chip, and part of the first semiconductor chip is not covered by the second semiconductor chip, and
- the first recessed region has a depth in a range from 90 μm to 780 μm, when measured from a lowermost surface of the first semiconductor substrate.
4 more elements
A semiconductor package, comprising:
- a package substrate;
- a first semiconductor chip on and electrically connected to the package substrate;
- a second semiconductor chip on the first semiconductor chip, the second semiconductor chip having a recessed region, in which the first semiconductor chip is inserted, so that the first semiconductor chip is between the package substrate and a protruding portion of the second semiconductor chip formed above the recessed region;
- a first wire connecting the second semiconductor chip to the package substrate;
- a third semiconductor chip on the second semiconductor chip;
- a second wire connecting the third semiconductor chip to the second semiconductor chip;
- and
- a first adhesive layer between the second semiconductor chip and the third semiconductor chip, an upper portion of the second wire being buried in the first adhesive layer.
5 more elements
Dependencies are inferred from the claim text.