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US 12,599,036 B2Granted
Circuit architecture in multi-dimensional monolithic structure
AssigneeArm Limited
InventorsLokesh Kumar Saini, Amit Chhabra, Valerio Lanieri
Life of this patent
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Abstract
Various implementations described herein are related to a device having a multi-transistor structure for use in circuit architecture. The multi-transistor structure may have a multi-transistor stack of at least one of N-type transistors or P-type transistors that are arranged in a multi-device stack configuration. Also, a physical layout of the multi-device stack configuration may provide a common-centroid configuration for process mismatch cancellation in at least one of the X-Y-Z axes.
Claims20
A device comprising:
- a multi-transistor structure for use in circuit architecture, wherein:
- the multi-transistor structure has a plurality of multi-transistor stacks of at least one of N-type transistors or P-type transistors that are each arranged in a multi-device stack configuration, and
- a physical layout of the plurality of multi-transistor stacks comprises a common-centroid configuration in at least one of X, Y, or Z axes to address process mismatch.
A device comprising:
- a multi-transistor structure for use in circuit architecture, wherein:
- the multi-transistor structure has a multi-transistor stack of N-type transistors or P-type transistors that are arranged in a first two-device stack configuration, and
- a physical layout of the first two-device stack configuration forms a common-centroid configuration with a second two-device stack configuration in at least one of X, Y, or Z axes to address process mismatch.
A device comprising:
- a multi-transistor structure for use in circuit architecture, wherein:
- the multi-transistor structure has a multi-transistor stack of N-type transistors or P-type transistors that are arranged in a first four-device stack configuration, and
- a physical layout of the first four-device stack configuration forms a common-centroid configuration with a second four-device stack configuration in at least one of X, Y, or Z axes to address process mismatch.
Dependencies are inferred from the claim text.