Microelectronic structure including active base substrate with through vias between a top die and a bottom die supported on an interposer

A semiconductor package, including:

• a package substrate;
• and
• a microelectronic component coupled to the package substrate, the microelectronic component including:
• a first substrate having first through vias therein, the first substrate including silicon or glass;
• a first layer on a front surface of the first substrate, the first layer including one or more first dies coupled to the first through vias;
• a second substrate on a front surface of first layer, the second substrate having second through vias therein and including silicon or glass;
• a second layer on a front surface of the second substrate such that the first layer is between the first substrate and the second substrate, the second layer including one or more second dies coupled to the second through vias;
• and
• electrically conductive structures on a back surface of the first substrate, the electrically conductive structures coupled to the first through vias at one side thereof, and to the package substrate at another side thereof, wherein at least one of:
• the second through vias have a pitch less than or equal to 2 μm and a diameter that is about ½ of the pitch;
• or
• the pitch is above 2 μm, the diameter is between about 5 μm and 10 μm.

An integrated circuit (IC) device assembly, including:

• a printed circuit board;
• and
• a plurality of integrated circuit components coupled to the printed circuit board, individual ones of the integrated circuit components including one or more semiconductor packages, individual ones of the semiconductor packages including:
• a package substrate;
• and
• a microelectronic component coupled to the package substrate, the microelectronic component including:
• a first substrate having first through vias therein, the first substrate including silicon or glass;
• a first layer on a front surface of the first substrate, the first layer including one or more first dies coupled to the first through vias;
• a second substrate on a front surface of first layer, the second substrate having second through vias therein and including silicon or glass;
• a second layer on a front surface of the second substrate such that the first layer is between the first substrate and the second substrate, the second layer including one or more second dies coupled to the second through vias;
• and
• electrically conductive structures on a back surface of the first substrate, the electrically conductive structures coupled to the first through vias at one side thereof, and to the package substrate at another side thereof wherein at least one of:
• the second through vias have a pitch less than or equal to 2 um and a diameter that is about of the pitch;
• or the pitch is above 2 pm, the diameter is between about 5 um and 10 um .

A method to form a microelectronic structure of a semiconductor package, the method including:

• providing a first microelectronic subassembly including a structure for a first wafer (first wafer structure) having first through vias therein, the first wafer structure including silicon or glass;
• providing a second microelectronic subassembly including:
• a structure for a second wafer (second wafer structure) including silicon or glass, the second wafer structure having second through vias therein;
• and
• a first layer on a back surface of the second wafer structure, the first layer including one or more first dies coupled to the second through vias;
• bonding the first microelectronic subassembly to the second microelectronic subassembly such that the one or more first dies are electrically coupled to the first wafer structure;
• removing a portion of the second wafer structure to yield a second wafer therefrom and to reveal the second through vias at a front surface of the second wafer;
• bonding a plurality of die assemblies to the second wafer such that dies of the die subassemblies are coupled to corresponding ones of the second through vias, the die subassemblies together defining a second layer;
• removing a portion of the first wafer structure to yield a first wafer therefrom and to reveal the first through vias at a back surface of the first wafer;
• providing electrically conductive structures coupled to the first through vias at the back surface of the first wafer to result in a microelectronic assembly including the first wafer the first layer, the second wafer and the die assemblies;
• and
• singulating through the microelectronic assembly in a direction from the die assemblies through the first wafer to yield a plurality microelectronic components, wherein individual ones of the first wafer and the second wafer yield, respectively, a plurality of first wafer and second wafers from singulation.