US 12,599,032 B2Granted

Bilayer memory stacking with lines shared between bottom and top memory layers

AssigneeIntel Corporation

InventorsAbhishek A. Sharma, Noriyuki Sato, Van H. Le, Sarah Atanasov, Hui Jae Yoo, Bernhard Sell, Pei-hua Wang, Travis W. Lajoie, Chieh-Jen Ku, Juan G. Alzate-Vinasco, Fatih Hamzaoglu

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Abstract

IC devices implementing bilayer stacking with lines shared between bottom and top memory layers, and associated systems and methods, are disclosed. An example IC device includes a support structure, a front end of line (FEOL) layer and a back end of line (BEOL) layer. The BEOL layer includes a first memory cell in a first layer over the support structure, an electrically conductive line in a second layer, above the first layer, and a second memory cell in a third layer, above the second layer. The line could be one of a wordline, a bitline, or a plateline that is shared between the first and second memory cells. In particular, bilayer stacking line sharing is such that only one line is provided as a line to be shared between one or more of the memory cells of the first layer and one or more memory cells of the third layer.

Claims20

Dependent claims

An integrated circuit (IC) device, comprising:

a substrate;
a first memory cell in a first layer over the substrate;
a line comprising an electrically conductive material, in a second layer over the substrate, where the first layer is between the second layer and the substrate;
and
a second memory cell in a third layer over the substrate, where the second layer is between the first layer and the third layer,
wherein:
the line includes a first face and a second face, the second face being opposite the first face and being further away from the substrate than the first face,
the first memory cell is coupled to the first face of the line and includes a first capacitor,
the second memory cell is coupled to the second face of the line and includes a second capacitor,
a channel material of a transistor of the first memory cell is closer to the first face of the line than to the second face of the line and is between the line and contacts of a source region and a drain region of the transistor of the first memory cell,
each of the first capacitor and the second capacitor includes an electrode having a U-shape, and
the U-shape of the first capacitor is oriented in the IC device upside down compared to the U-shape of the second capacitor.

9 more elements

An integrated circuit (IC) package, comprising:

an IC device;
and
a further IC component, coupled to the IC device,
wherein the IC device includes:
a die,
a first memory cell in a first layer over the die,
a first line comprising an electrically conductive material, in a second layer over the die, where the first layer is between the second layer and the die,
a second memory cell in a third layer over the die, where the second layer is between the first layer and the third layer,
a second line comprising an electrically conductive material, in a fourth layer over the die, where the third layer is between the second layer and the fourth layer, and
a third memory cell in a fifth layer over the die, where the fourth layer is between the third layer and the fifth layer,
wherein:
each of the first memory cell and the second memory cell is coupled to the first line,
each of the second memory cell and the third memory cell is coupled to the second line,
the first memory cell includes a first capacitor,
the second memory cell includes a second capacitor,
each of the first capacitor and the second capacitor includes an electrode having a U-shape, and
the U-shape of the first capacitor is oriented in the IC device upside down compared to the U-shape of the second capacitor.

14 more elements

Dependencies are inferred from the claim text.