# US 12,599,016 B2 · Flip chip package

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- Number: US 12,599,016 B2
- Document ID: US12599016B2
- Status: Granted
- Kind: B2
- Application number: 18/363,275
- Filed: 2023-08-01
- Published: 2025-02-06
- Granted: 2026-04-07
- Earliest claimed: 2023-08-01
- Assignees: Dell Products L.P.
- Applicants: Dell Products L.P.
- Inventors: Qinghong He; Isaac Qin Wang
- Web page: https://patentgrep.com/patent/US12599016B2

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H01R 12/79: connecting to rigid printed circuits or like structures
- H01R 43/26: for engaging or disengaging the two parts of a coupling device (structural association with two-part coupling device H01R13/629)
- H05K 1/181: associated with surface mounted components
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/685: comprising multiple insulating layers
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H05K 2201/10356: Cables
- H10W 72/072: {of bump connectors}
- H10W 72/30: Die-attach connectors
- H10W 72/851: {Dispositions of multiple connectors or interconnections}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H01R: ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

In one or more embodiments, a chip may be formed with a first set of contacts on a first surface layer and a second set of contacts on a second surface layer opposite the first surface layer. The first set of contacts may be communication (IO) contacts and the second set of contacts may be power contacts, including ball grid array (BGA) balls and capacitors. A PCB may be configured with a chip receiving area capable of receiving the second set of contacts for various chips.

## Claims

### Claim 1

A chip package, comprising:
a substrate, comprising:
a first via;
a second via;
a third via;
a fourth via;
a first trace connected between the first via and the second via;
a second trace connected between the third via and the fourth via;
a plurality of layers, including:
a first surface layer of the plurality of layers comprises a first set of contacts, wherein each contact in the first set of contacts is a first contact type, a particular first contact of the first set of contacts connected to the first via; and
a second surface layer of the plurality of layers opposite the first surface layer comprises a second set of contacts, wherein each contact in the second set of contacts is a second contact type that is different than the first contact type, a particular second contact of the second set of contacts connected to the fourth via; and
a silicon die mounted to the first surface layer;
a first power contact positioned between the silicon die and the first surface layer, and in contact with the second via;
a second power contact positioned between the silicon die and the first surface layer, and in contact with the third via;
wherein the particular first contact at the first surface layer is connected to the first power contact through the first via, the first trace and the second via,
wherein the particular second contact at the second surface layer is connected to the second power contact through the fourth via, the second trace, and the third via.

### Claim 2 (depends on 1)

The chip package of claim 1, wherein the first set of contacts comprises input/output (I/O) contacts.

### Claim 3 (depends on 1)

The chip package of claim 1, wherein the first set of contacts is arranged proximate an edge of the substrate.

### Claim 4 (depends on 3)

The chip package of claim 3, wherein the substrate is substantially rectangular and defined by two end edges and two side edges, wherein the two side edges are longer than the two end edges, wherein the first set of contacts is arranged proximate to a side edge of the substrate.

### Claim 5 (depends on 3)

The chip package of claim 3, wherein the substrate is substantially rectangular and defined by two end edges and two side edges, wherein the two side edges are longer than the two end edges, wherein the first set of contacts is arranged proximate to an end edge of the substrate.

### Claim 6 (depends on 1)

The chip package of claim 1, further comprising a first surface mount connector coupled to the first set of contacts.

### Claim 7 (depends on 1)

The chip package of claim 1, wherein the second set of contacts comprises power contacts.

### Claim 8

A system comprising:
a printed circuit board (PCB) with a mainboard connector;
a chip package comprising:
a substrate, comprising:
a first via;
a second via;
a third via;
a fourth via;
a first trace connected between the first via and the second via;
a second trace connected between the third via and the fourth via;
a plurality of layers, including:
a first surface layer of the plurality of layers comprises a first set of contacts, wherein each contact in the first set of contacts is a first contact type, a particular first contact of the first set of contacts connected to the first via; and
a second surface layer of the plurality of layers opposite the first surface layer comprises a second set of contacts, wherein each contact in the second set of contacts is a second contact type that is different than the first contact type, a particular second contact of the second set of contacts connected to the fourth via; and
a silicon die mounted to the first surface layer;
a first power contact positioned between the silicon die and the first surface layer, and in contact with the second via;
a second power contact positioned between the silicon die and the first surface layer, and in contact with the third via;
wherein the particular first contact at the first surface layer is ultimately connected to the first power contact through the first via, the first trace and the second via,
wherein the particular second contact at the second surface layer is ultimately connected to the second power contact through the fourth via, the second trace, and the third via,
a connector coupling the first set of contacts to the mainboard connector.

### Claim 9 (depends on 8)

The chassis of claim 8, wherein the first set of contacts comprises input/output (I/O) contacts.

### Claim 10 (depends on 8)

The chassis of claim 8, wherein the first set of contacts is arranged proximate an edge of the substrate.

### Claim 11 (depends on 10)

The chassis of claim 10, wherein the substrate is substantially rectangular and defined by two end edges and two side edges, wherein the two side edges are longer than the two end edges, wherein the first set of contacts is arranged proximate to a side edge of the substrate.

### Claim 12 (depends on 10)

The chassis of claim 10, wherein the substrate is substantially rectangular and defined by two end edges and two side edges, wherein the two side edges are longer than the two end edges, wherein the first set of contacts is arranged proximate to an end edge of the substrate.

### Claim 13 (depends on 8)

The chassis of claim 8, wherein the connector coupling the first set of contacts to the mainboard connector comprises:
a surface mount connector mounted on the substrate; and
a cable connecting the surface mount connector to the mainboard connector.

### Claim 14 (depends on 8)

The chassis of claim 8, wherein the connector coupling the first set of contacts to the mainboard connector comprises:
a compression connector mounted on the substrate; and
a cable connecting the surface mount connector to the mainboard connector.

### Claim 15

A method of connecting a chip package to a printed circuit board (PCB), the method comprising:
forming a substrate, comprising:
forming a first via, a second via, a third via, and a fourth via;
forming a first trace connected between the first via and the second via;
forming a second trace connected between the third via and the fourth via;
forming a first surface layer of the plurality of layers with a first set of contacts, wherein each contact in the first set of contacts is a first contact type a particular first contact of the first set of contacts connected to the first via; and
forming a second surface layer of the plurality of layers opposite the first surface layer with a second set of contacts, wherein each contact in the second set of contacts is a second contact type that is different than the first contact type, a particular second contact of the second set of contacts connected to the fourth via;
mounting a silicon die to the first surface layer,
wherein a first power contact is positioned between the silicon die and the first surface layer, and in contact with the second via;
wherein a second power contact is positioned between the silicon die and the first surface layer, and in contact with the third via;
mounting the substrate in a chip receiving area on a PCB, wherein the second set of contacts are connected to chip connection points;
contacting a first end of a connector to the first set of contacts; and
contacting a second end of the connector to a mainboard connector on the PCB,
wherein the particular first contact at the first surface layer is ultimately connected to the first power contact through the first via, the first trace and the second via,
wherein the particular second contact at the second surface layer is ultimately connected to the second power contact through the fourth via, the second trace, and the third via.

### Claim 16 (depends on 15)

The method of claim 15, wherein the connector comprises a flexible cable.

### Claim 17 (depends on 15)

The method of claim 15, wherein:
contacting the first end of the connector to the first set of contacts comprises:
positioning a compression connector relative to the first set of contacts; and
contacting a first end of a board connector with the compression connector; and
contacting the second end of the connector to the mainboard connector on the PCB comprises contacting a second end of the board connector to the mainboard connector.

### Claim 18 (depends on 15)

The method of claim 15, wherein forming the first surface layer of the plurality of layers with the first set of contacts comprises forming the first set of contacts proximate an end edge of the substrate.

### Claim 19 (depends on 15)

The method of claim 15, wherein forming the first surface layer of the plurality of layers with the first set of contacts comprises forming the first set of contacts proximate a side edge of the substrate.

### Claim 20 (depends on 15)

The method of claim 15, wherein forming the first surface layer of the plurality of layers with the first set of contacts comprises forming the first set of contacts proximate two or more edges of the substrate.