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US 12,599,008 B2Granted
Transistor with source manifold in non-active die region
AssigneeNXP USA, Inc.
InventorsHumayun Kabir, Ibrahim Khalil
Life of this patent
Estimating the term…
Abstract
A transistor includes a semiconductor die with an active region and one or more non-active regions that do not overlap or overlie the active region. The transistor further includes a group of multiple transistor fingers in the active region. One or more source vias are located adjacent to sides of the group of transistor fingers. One or more source manifolds are located in the non-active region(s), and the source manifold(s) electrically connect the source via(s) with at least one source region of the multiple transistor fingers.
Claims18
A transistor comprising:
- a semiconductor die with top and bottom surfaces, and first, second, third, and fourth sides, wherein the first and third sides are parallel to each other, and wherein the second and fourth sides are parallel to each other, and wherein the semiconductor die further includes a base substrate, a build-up structure overlying an upper surface of the base substrate, an active region that extends between the bottom and top surfaces of the semiconductor die, and a first non-active region that extends between the bottom and top surfaces of the semiconductor die and that does not overlap or overlie the active region;
- an input terminal between the active region and the first side of the semiconductor die;
- an output terminal between the active region and the third side of the semiconductor die;
- a first group of multiple transistor fingers in the active region, wherein the first group of multiple transistor fingers includes a first transistor finger with a first elongated source region in the base substrate, and a first elongated source contact connected to the first elongated source region and formed from a first portion of a conductive contact layer;
- a first source via located next to the first group of multiple transistor fingers and between the second side of the semiconductor die and the first group of multiple transistor fingers;
- a first source manifold located in the first non-active region, wherein the first source manifold electrically connects the first source via with at least one source region of the multiple transistor fingers of the first group of multiple transistor fingers;
- a first source strip overlying and electrically coupled to the first elongated source contact in the active region;
- a first source strip extension that extends from the first source strip into the first non-active region over the first source manifold;
- and
- a first vertical conductive structure coupled between the first source strip extension and the first source manifold, wherein the first vertical conductive structure is formed from a stackup of conductive layers between the first source strip extension and the first source manifold.
7 more elements
A transistor comprising:
- a semiconductor die with top and bottom surfaces, and first, second, third, and fourth sides, wherein the first and third sides are parallel to each other, and wherein the second and fourth sides are parallel to each other, and wherein the semiconductor die further includes a base substrate, a build-up structure overlying an upper surface of the base substrate, an active region that extends between the bottom and top surfaces of the semiconductor die, and a first non-active region that extends between the bottom and top surfaces of the semiconductor die and that does not overlap or overlie the active region;
- an input terminal between the active region and the first side of the semiconductor die;
- an output terminal between the active region and the third side of the semiconductor die;
- a first group of multiple transistor fingers in the active region, wherein the first group of multiple transistor fingers includes:
- a first transistor finger with a first elongated source region in the base substrate, a first elongated drain region in the base substrate, a first elongated channel region in the base substrate between the first elongated source region and the first elongated drain region, a first elongated gate structure over the first elongated channel region, and a first elongated source contact connected to the first elongated source region and formed from a first portion of a conductive contact layer, and
- a second transistor finger with a second elongated source region in the base substrate, a second elongated drain region in the base substrate, a second elongated channel in the base substrate between the second elongated source region and the second elongated drain region, a second elongated gate structure over the second elongated channel, and a second elongated source contact connected to the second elongated source region and formed from a second portion of the conductive contact layer;
- a first source via located next to the first group of multiple transistor fingers and between the second side of the semiconductor die and the first group of multiple transistor fingers;
- and
- a first source manifold located in the first non-active region, wherein the first source manifold electrically connects the first source via with at least one source region of the multiple transistor fingers of the first group of multiple transistor fingers;
- a first source strip overlying and electrically coupled to the first elongated source contact in the active region;
- a first source strip extension that extends from the first source strip into the first non-active region over the first source manifold;
- a first vertical conductive structure coupled between the first source strip extension and a first point along the first source manifold;
- a second source strip overlying and electrically coupled to the second elongated source contact in the active region;
- a second source strip extension that extends from the second source strip into the first non-active region over the first source manifold;
- and
- a second vertical conductive structure coupled between the second source strip extension and a second point along the first source manifold that is spatially-separated from the first point.
13 more elements
A transistor comprising:
- a semiconductor die with top and bottom surfaces, an active region that extends between the bottom and top surfaces of the semiconductor die, and a first non-active region that extends between the bottom and top surfaces of the semiconductor die and that does not overlap or overlie the active region;
- a first group of multiple transistor fingers in the active region;
- a first source via located adjacent to a first side of the first group of multiple transistor fingers;
- a second source via located adjacent to a second side of the first group of multiple transistor fingers;
- and
- a first source manifold located in the first non-active region, wherein the first source manifold electrically connects the first and second source vias with multiple source regions of the multiple transistor fingers of the first group of multiple transistor fingers, and wherein the first source manifold is divided into first and second segments that are separated by a non-conductive gap, wherein the first segment is electrically coupled to the first source via, the second segment is electrically coupled to the second source via, a first group of the multiple transistor fingers is coupled to the first segment, and a second group of the multiple transistor fingers is coupled to the second segment.
3 more elements
Dependencies are inferred from the claim text.