# US 12,599,007 B2 · Composite IC die package including an electro-thermo-mechanical die (ETMD) with through substrate vias

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- Number: US 12,599,007 B2
- Document ID: US12599007B2
- Status: Granted
- Kind: B2
- Application number: 17/560,609
- Filed: 2021-12-23
- Published: 2023-06-29
- Granted: 2026-04-07
- Earliest claimed: 2021-12-23
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Debendra Mallik; Omkar Karhade; Nitin Deshpande
- Web page: https://patentgrep.com/patent/US12599007B2

## CPC

- H10W 70/611: {for connecting multiple chips together}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/685: comprising multiple insulating layers
- H10W 72/90: Bond pads, in general
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/20: Configurations of stacked chips
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Multi-die composite packages including directly bonded IC die and at least one electro-thermo-mechanical die (ETMD). An ETMD is distinguished from an active IC die as an ETMD is a passive die lacking any semiconductor devices, such as transistors. In exemplary embodiments, an ETMD includes a substrate, which may be a crystalline semiconductor material, for example, and one or more through substrate vias (TSVs) passing through a thickness of the substrate. The TSVs may enable a ETMD to electrically interconnect an (active) IC die of a composite package to another IC die of the package or to a package host.

## Claims

### Claim 1

An integrated circuit (IC) die package comprising:
a first IC die;
a passive die directly bonded to a first portion of a first side of the first IC die, wherein the passive die lacks a device layer, but comprises routing metallization on a first side and one or more through vias extending to corresponding interconnect interfaces on a second side of the passive die; and
a second IC die adjacent to the passive die and directly bonded to a second portion of the first side of the first IC die.

### Claim 2 (depends on 1)

The IC die package of claim 1, wherein the second IC die comprises through vias coupled to corresponding second interconnect interfaces on a second side of the second IC die, and wherein the interconnect interfaces are co-planar with the second interconnect interfaces.

### Claim 3 (depends on 1)

The IC die package of claim 1, further comprising an inorganic dielectric in contact with a third portion of the first side of the first IC die, the third portion between the first and second portions.

### Claim 4 (depends on 3)

The IC die package of claim 3, wherein the inorganic dielectric comprises a compound comprising nitrogen.

### Claim 5 (depends on 1)

The IC die package of claim 1, further comprising a package insulator material substantially filling a space between the passive die and the second IC die.

### Claim 6

A system comprising:
a host component;
an integrated circuit (IC) die package comprising:
a first IC die with first interconnect interfaces on a first side of the first IC die;
a passive die directly bonded to a first portion of the first side of the first IC die, wherein the passive die lacks a device layer, but comprises routing metallization coupled to second interconnect interfaces on a first side of the passive die, and one or more through vias extending from the routing metallization to corresponding third interconnect interfaces on a second side of the passive die, wherein the second interconnect interfaces are in direct contact with first ones of the first interconnect interfaces; and
a second IC die adjacent to the passive die and directly bonded to a second portion of the first side of the first IC die, wherein the second IC die comprises fourth interconnect interfaces on a first side of the second IC die and in direct contact with second ones of the first interconnect interfaces, and wherein the second IC die comprises through vias extending to fifth interconnect interfaces on a second side of the second IC die; and
solder features, wherein a first ones of the solder features are in contact with a first portion of the host component and in contact with the third interconnect interfaces, and wherein second ones of the solder features are in contact with a second portion of the host component and in contact with the fifth interconnect interfaces.

### Claim 7 (depends on 6)

The system of claim 6, further comprising:
a power supply coupled to the host component to send power through the passive die.

### Claim 8 (depends on 6)

The system of claim 6, wherein:
the first IC die is a first of a microprocessor core circuitry, wireless radio circuitry, floating point gate array (FPGA) circuitry, power management circuitry, active repeater circuitry, clock generator circuitry, memory circuitry, or input/output buffer circuitry; and
the second IC die is a second of a microprocessor core circuitry, wireless radio circuitry, floating point gate array (FPGA) circuitry, power management circuitry, active repeater circuitry, clock generator circuitry, memory circuitry, or input/output buffer circuitry.

### Claim 9 (depends on 1)

The IC die package of claim 1, wherein:
the first IC die comprises first interconnect interfaces on a first side of the first IC die;
the passive die comprises second interconnect interfaces on the first side of the passive die, and in direct contact with first ones of the first interconnect interfaces;
the passive die comprises third interconnect interfaces on the second side of the passive die;
the second IC die comprises fourth interconnect interfaces on a first side of the second IC die and in direct contact with second ones of the first interconnect interfaces; and
the second IC die comprises fifth interconnect interfaces on the second side of the second IC die.

### Claim 10 (depends on 9)

The IC die package of claim 9, further comprising:
first solder features in contact with the third interconnect interfaces; and
second solder features in contact with the fifth interconnect interfaces.

### Claim 11 (depends on 10)

The IC die package of claim 10, further comprising a single host component, wherein a first portion of the host component is in contact with the first solder features and a second portion of the host component is in contact with the second solder features.

### Claim 12 (depends on 9)

The IC die package of claim 9, wherein the first ones of the first interconnect interfaces are metallurgically interdiffused with the second interconnect interfaces and wherein the second ones of the first interconnect interfaces are metallurgically interdiffused with the fourth interconnect interfaces.

### Claim 13 (depends on 3)

The IC die package of claim 3, wherein the inorganic dielectric is a conformal layer comprising nitrogen and silicon, and further comprising an organic material within topography traversed by the conformal layer of inorganic dielectric.

### Claim 14 (depends on 13)

The IC die package of claim 13, wherein the organic material is an epoxy with one or more filler.

### Claim 15 (depends on 9)

The IC die package of claim 9, wherein the third and fifth interconnect interfaces are coplanar.

### Claim 16 (depends on 1)

The IC die package of claim 1, wherein both the IC die and the passive die comprise a substrate material, the substrate material is silicon, the through vias of the IC die extend through the silicon substrate material of the IC die, and the through vias of the passive die extend through the silicon substrate material of the passive die.