Back to results
US 12,598,983 B2Granted
Interconnects formed using integrated damascene and subtractive etch processing
AssigneeInternational Business Machines Corporation
InventorsNicholas Anthony Lanzillo, Huai Huang, Hosadurga Shobha, Lawrence A. Clevenger
Life of this patent
Estimating the term…
Abstract
A semiconductor structure comprises two or more interconnect lines of a first width in a given interconnect level, and two or more interconnect lines of a second width in the given interconnect level. The two or more interconnect lines of the second width are disposed between a first one of the two or more interconnect lines of the first width and a second one of the two or more interconnect lines of the second width. The two or more interconnect lines of the first width have sidewalls with a negative taper angle. The two or more interconnect lines of the second width have sidewalls with a positive taper angle.
Claims20
A semiconductor structure comprising:
- two or more interconnect lines of a first width in a given interconnect level;
- and
- two or more interconnect lines of a second width in the given interconnect level;
- wherein the two or more interconnect lines of the second width are disposed between a first one of the two or more interconnect lines of the first width and a second one of the two or more interconnect lines of the second width;
- wherein the two or more interconnect lines of the first width have sidewalls with a negative taper angle;
- wherein the two or more interconnect lines of the second width have sidewalls with a positive taper angle;
- wherein the first one of the two or more interconnect lines of the first width comprises a bottom via structure in the given interconnect level that is coincident with bottom portions of each of the two or more interconnect lines of the second width in the given interconnect level;
- and
- wherein the second one of the two or more interconnect lines of the first width comprises a bottom via structure in the given interconnect level that is not coincident with the bottom portions of any of the two or more interconnect lines of the second width in the given interconnect level.
6 more elements
An integrated circuit, comprising:
- a back-end-of-line interconnect structure comprising two or more interconnect levels;
- wherein at least a given one of the two or more interconnect levels comprises:
- two or more interconnect lines of a first width;
- and
- two or more interconnect lines of a second width;
- wherein the two or more interconnect lines of the second width are disposed between a first one of the two or more interconnect lines of the first width and a second one of the two or more interconnect lines of the second width;
- wherein the two or more interconnect lines of the first width have sidewalls with a negative taper angle;
- wherein the two or more interconnect lines of the second width have sidewalls with a positive taper angle;
- wherein the first one of the two or more interconnect lines of the first width comprises a bottom via structure in the given interconnect level that is coincident with bottom portions of each of the two or more interconnect lines of the second width in the given interconnect level;
- and
- wherein the second one of the two or more interconnect lines of the first width comprises a bottom via structure in the given interconnect level that is not coincident with the bottom portions of any of the two or more interconnect lines of the second width in the given interconnect level.
8 more elements
A method comprising:
- forming two or more interconnect lines of a first width in a given interconnect level;
- and
- forming two or more interconnect lines of a second width in the given interconnect level;
- wherein the two or more interconnect lines of the second width are disposed between a first one of the two or more interconnect lines of the first width and a second one of the two or more interconnect lines of the second width;
- wherein the two or more interconnect lines of the first width have sidewalls with a negative taper angle;
- wherein the two or more interconnect lines of the second width have sidewalls with a positive taper angle;
- wherein the first one of the two or more interconnect lines of the first width comprises a bottom via structure in the given interconnect level that is coincident with bottom portions of each of the two or more interconnect lines of the second width in the given interconnect level;
- and
- wherein the second one of the two or more interconnect lines of the first width comprises a bottom via structure in the given interconnect level that is not coincident with the bottom portions of any of the two or more interconnect lines of the second width in the given interconnect level.
6 more elements
Dependencies are inferred from the claim text.