Fill of vias in single and dual damascene structures using self-assembled monolayer
AssigneeIntel Corporation
InventorsJiun-Ruey Chen, Christopher Jezewski, John Plombon, Miriam Reshotko, Mauro Kobrinsky, Scott B. Clendenning
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Abstract
Metallization interconnect structures, integrated circuit devices, and methods related to high aspect ratio interconnects are discussed. A self assembled monolayer is selectively formed on interlayer dielectric sidewalls of an opening that exposes an underlying metallization structure. A first metal is formed on the underlying metallization structure and within only a bottom portion of the self assembled monolayer. The exposed portion of the self assembled monolayer is removed and a second metal is formed over the first metal.
Claims22
An integrated circuit device, comprising:
- a first metallization level comprising a metallization feature;
- a second metallization level over the first metallization level, the second metallization level comprising a metal via on the metallization feature and a metal line on the metal via, wherein the metal via and the metal line are within an interlayer dielectric material, the metal via comprising a first portion on the metallization feature and a second portion on the first portion, the first portion comprising a first metal and the second portion comprising the first metal or a second metal;
- and
- a layer between the first portion of the metal via and the interlayer dielectric material, the layer comprising a plurality of molecules having at least head groups coupled to the interlayer dielectric material and tails distal the interlayer dielectric material, wherein the second portion of the metal via is on the interlayer dielectric material and the first portion has a width that is less than a width of the second portion.
An integrated circuit device, comprising:
- a first metallization level comprising a metallization feature;
- a second metallization level comprising a metal via and a metal line within an interlayer dielectric material, the metal via comprising a first portion on the metallization feature and a second portion on the first portion, the first portion comprising a first metal and the second portion comprising the first metal or a second metal;
- and
- a layer between the first portion and the interlayer dielectric material, the layer comprising a plurality of molecules having at least head groups coupled to the interlayer dielectric material and tails distal the interlayer dielectric material, wherein the second portion is on the interlayer dielectric material, and the first portion has a width that is less than a width of the second portion.
Dependencies are inferred from the claim text.