Microelectronic devices, and related memory devices, electronic systems, and methods

A microelectronic device, comprising:

• a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers, the stack structure divided into blocks separated from one another by filled slot structures, each of the blocks comprising:
• a memory array region;
• staircase structures having steps comprising horizontal ends of at least some of the tiers of the stack structure;
• and
• crest regions interposed in a first horizontal direction between horizontally neighboring pairs of the staircase structures within the blocks, a first crest region of the crest regions interposed in the first horizontal direction between the memory array region and a first of the staircase structures, the first crest region comprising:
• a section relatively more horizontally proximate the first of the staircase structures;
• and
• an additional section relatively more horizontally proximate the memory array region;
• and
• contact structures within the first crest region of each of the blocks and vertically extending through the stack structure to a source tier underlying the stack structure, the contact structures arranged in rows extending in the first horizontal direction and columns extending in a second horizontal direction orthogonal to the first horizontal direction, the contact structures comprising:
• first contact structures in electrical communication with control logic circuitry;
• and
• second contact structures electrically isolated from the control logic circuitry, at least some of the first contact structures relatively more centrally positioned with each of the blocks in the second horizontal direction than at least some of the second contact structures;
• wherein:
• rows of the contact structures most horizontally to the proximate the filled slot structures include the second contact structures;
• and
• additional rows of the contact structures include the first contact structures, portions of the additional rows of the contact structures within the additional section of the first crest region only including the first contact structures.

A microelectronic device, comprising:

• a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers, the stack structure divided into blocks separated from one another by filled slot structures, each of the blocks comprising:
• a memory array region;
• staircase structures having steps comprising horizontal ends of at least some of the tiers of the stack structure;
• and
• crest regions interposed in a first horizontal direction between horizontally neighboring pairs of the staircase structures within the blocks, a first crest region of the crest regions interposed in the first horizontal direction between the memory array region and a first of the staircase structures;
• contact structures within the first crest region of each of the blocks and vertically extending through the stack structure to a source tier underlying the stack structure, the contact structures comprising:
• first contact structures in electrical communication with control logic circuitry;
• and
• second contact structures electrically isolated from the control logic circuitry, at least some of the first contact structures relatively more centrally positioned with each of the blocks in a second horizontal direction orthogonal to the first horizontal direction than at least some of the second contact structures;
• first conductive structures within the source tier and in physical contact with the first contact structures;
• and
• second conductive structures within the source tier and in physical contact with the second contact structures, the second conductive structures electrically isolated from the first conductive structures.

A microelectronic device, comprising:

• a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers, the stack structure divided into blocks separated from one another by filled slot structures, each of the blocks comprising:
• a memory array region;
• staircase structures having steps comprising horizontal ends of at least some of the tiers of the stack structure;
• and
• crest regions interposed in a first horizontal direction between horizontally neighboring pairs of the staircase structures within the blocks, a first crest region of the crest regions interposed in the first horizontal direction between the memory array region and a first of the staircase structures;
• contact structures within the first crest region of each of the blocks and vertically extending through the stack structure to a source tier underlying the stack structure, the contact structures comprising:
• first contact structures in electrical communication with control logic circuitry;
• and
• second contact structures electrically isolated from the control logic circuitry, at least some of the first contact structures relatively more centrally positioned with each of the blocks in a second horizontal direction orthogonal to the first horizontal direction than at least some of the second contact structures;
• and
• conductive routing structures vertically overlying and in electrical communication with the first contact structures, at least one of the conductive routing structures coupled to a different group of the first contact structures than at least one other of the conductive routing structures.

A memory device, comprising:

• a stack structure comprising tiers each comprising conductive material and insulative material vertically adjacent the conductive material, the stack structure divided into blocks separated from one another by dielectric-filled slot structures, at least one of the blocks comprising:
• a memory array region comprising strings of memory cells vertically extending through the stack structure;
• staircase structures comprising edges of the tiers;
• crest regions horizontally interposed between horizontally neighboring staircase structures, one of the crest regions horizontally interposed between the memory array region and a vertically highest one of the staircase structures;
• and
• bridge regions extending from and between the crest regions in a first horizontal direction and neighboring the staircase structures in a second horizontal direction;
• data lines overlying the stack structure and in electrical communication with the strings of memory cells;
• a source tier underlying the stack structure and comprising a source structure in electrical communication with the strings of memory cells;
• a control device underlying the source tier and comprising control logic circuitry in electrical communication with the data lines and the source structure;
• and
• contact structures within the one of the crest regions of the at least one of the blocks and vertically extending through the stack structure and into the source tier, the contact structures comprising:
• first contact structures in electrical communication with the control logic circuitry of the control device,
• multiple of the first contact structures ganged together by way of conductive routing structures overlying the stack structure, and
• multiple other of the first contact structures ganged together by way of additional conductive routing structures overlying the stack structure;
• and
• second contact structures electrically isolated from the control logic circuitry of the control device, at least some of the first contact structures relatively more horizontally distal from the dielectric-filled slot structures than at least some of the second contact structures.

An electronic system, comprising:

• an input device;
• an output device;
• a processor device operably coupled to the input device and the output device;
• and
• a memory device operably coupled to the processor device and comprising at least one microelectronic device structure comprising:
• a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers, the stack structure divided into blocks separated from one another by filled slot structures, the blocks individually comprising:
• a memory array region comprising vertically extending strings of memory cells;
• staircase structures having steps comprising horizontal ends of at least some of the tiers;
• crest regions horizontally interposed between horizontally neighboring ones of the staircase structures, a first of the crest regions horizontally interposed between the memory array region and a first of the staircase structures and comprising:
• a section relatively more horizontally proximate the first of the staircase structures;
• and
• an additional section relatively more horizontally proximate the memory array region;
• and
• bridge regions horizontally neighboring the staircase structures and horizontally extending from and between the crest regions;
• digit lines coupled with the vertically extending of memory cells;
• a source tier comprising a source structure coupled with the vertically extending strings of memory cells;
• control logic circuitry coupled with the digit lines and the source structure;
• and
• contact structures within the first of the crest regions of the blocks of the stack structure and extending through the stack structure and into the source tier, the contact structures arranged in rows extending in a first horizontal direction and columns extending in a second horizontal direction orthogonal to the first horizontal direction, the contact structures comprising:
• first contact structures in electrical communication with the control logic circuitry;
• and
• second contact structures electrically isolated from the control logic circuitry, at least some of the first contact structures relatively more horizontally offset from horizontal boundaries of the blocks than at least some of the second contact structures;
• wherein:
• rows of the contact structures most horizontally to the proximate the filled slot structures include the second contact structures;
• additional rows of the contact structures include the first contact structures;
• at least one of the columns of the contact structures within the section only includes the second contact structures;
• at least one other of the columns of the contact structures within the section includes the first contact structures and the second contact structures;
• and
• at least one further of the columns of the contact structures within the additional section includes the first contact structures and the second contact structures.