Methods used in forming a memory array comprising strings of memory cells including insulator walls in a through-array-via region

A method used in forming a memory array comprising strings of memory cells, comprising:

• forming a conductor tier directly above a lower tier, the conductor tier comprising an upper conductor material and a lower conductor material, the lower tier being disposed over a horizontal upper surface of a substrate and comprising conductive lines that are horizontally elongated along a first direction and spaced horizontally from adjacent of the conductive lines along a second direction by a dielectric material, an insulator tier being vertically between the conductor tier and the lower tier;
• forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers above the conductor tier;
• the lower portion, the conductor tier, the insulator tier, and the lower tier collectively comprising laterally-spaced memory-block regions and a through-array-via (TAV) region, the TAV region comprising lower vias that individually extend through the insulator tier and directly electrically couple to one of the conductive lines;
• forming insulator walls in the TAV region, the insulator walls extending from the lower portion through the conductor tier and the insulator tier and into the dielectric material within the lower tier and being horizontally elongated, a portion of the insulator walls being disposed between adjacent of the conductive lines along the second direction;
• after forming the insulator walls, forming the vertically-alternating different-composition first tiers and second tiers of an upper portion of the stack above the lower portion and above all portions of the insulator walls, and forming channel-material strings that extend through the first tiers and the second tiers in the upper portion to the lower portion and that directly electrically couple to conductor material in the conductor tier, the insulator walls individually extending horizontally past a plurality of the channel-material strings;
• forming upper vias in the TAV region directly above and that individually extend to directly electrically couple to individual of the lower vias to form individual TAVs;
• and
• the memory-block regions comprising memory blocks and horizontally-elongated isolation structures between individual of the memory blocks, the memory-block regions individually comprising multiple of the channel-material strings, the isolation structures individually extending horizontally past the plurality of the channel-material strings, the insulator walls being structurally different from the isolation structures and having bottommost surfaces that are lower than bottommost surfaces of the isolation structures.