Hardmask integration for high aspect ratio applications
AssigneeTokyo Electron Limited
InventorsJoshua Baillargeon, Jinying Lin
Life of this patent
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Abstract
A method for fabricating semiconductor devices is disclosed. The method includes forming a stack over a substrate. The method includes forming a hardmask layer over the stack, the hardmask layer comprising a first tungsten containing sub-layer, and at least one compressive sub-layer and at least one tensile sub-layer. The method includes forming a patternable layer over the hardmask layer. The method includes etching the hardmask layer according to the patternable layer.
Claims18
A method for fabricating a semiconductor device, comprising:
- forming a stack over a substrate;
- forming a hardmask layer over the stack, the hardmask layer comprising a first tungsten containing sub-layer, the hardmask layer including at least one compressive sub-layer and at least one tensile sub-layer;
- forming a patternable layer over the hardmask layer;
- and
- etching the hardmask layer according to the patternable layer to form an opening comprising an upper portion of a reentrant cavity disposed vertically above the stack and a lower portion comprising a first sidewall and a second sidewall opposite the first sidewall, a distance between the first sidewall and the second sidewall monotonically decreasing between an upper surface of the stack and the substrate of the semiconductor device.
A method, for fabricating semiconductor devices, comprising:
- forming a first tungsten-based layer over an upper surface of a semiconductor device stressed in a first mode;
- forming a nitride layer stressed in a second mode opposite the first mode;
- forming a second tungsten-based layer over the upper surface of a semiconductor device stressed in the first mode;
- forming a patternable layer over the second tungsten-based layer;
- etching the semiconductor device to form an opening through each of the first tungsten-based layer, the nitride layer, and the second tungsten-based layer, wherein the etching forms a reentrant cavity extending no lower than the first tungsten-based layer;
- and
- removing the first tungsten-based layer, the nitride layer, and the second tungsten-based layer.
A method for fabricating a memory device, comprising:
- (a) forming a stack over a substrate;
- (b) forming a compressive layer over the substrate;
- (c) forming a tensile layer over the substrate;
- (d) alternating between each of (b) and (c) such that:
- a total compressive stress exceeds a first stress constraint for the substrate;
- a total tensile stress exceeds a second stress constraint for the substrate;
- and
- a net stress does not exceed the first stress constraint or the second stress constraint;
- and
- (e) etching the memory device from an upper surface to the stack, wherein the etching extends an opening though the stack, and includes forming a reentrant cavity disposed vertically above the stack.
Dependencies are inferred from the claim text.