Methods of manufacturing semiconductor devices using enhanced patterning techniques

A method of manufacturing a semiconductor device, comprising:

• forming a substrate having first and second regions therein with unequal densities of active regions in the first and second regions;
• forming a cell trench defining cell active regions in the first region and a peripheral trench defining peripheral active regions in the second region;
• forming a first insulating layer in the cell trench and in the peripheral trench;
• forming a mask that covers the first insulating layer in the first region, but exposes the first insulating layer in the second region;
• forming a second insulating layer on a portion of the first insulating layer in the second region that is exposed by the mask, using a dielectric-on-dielectric selective deposition process;
• after forming the second insulating layer, exposing the first insulating layer in the first region by removing the mask;
• and
• forming a third insulating layer on the first insulating layer in the first region and on the second insulating layer in the second region.

A method of manufacturing a semiconductor device, the method comprising:

• forming a substrate having first and second regions therein, which contain unequal densities of active regions in the first and second regions;
• forming a cell trench that defines cell active regions in the first region, a first cell trench portion having a relatively narrow width in the first region, and a second cell trench portion having a relatively wide width in the first region;
• forming a peripheral trench that defines peripheral active regions in the second region, a first peripheral trench portion having a relatively narrow width in the second region, and a second peripheral trench portion having a relatively wide width in the second region;
• forming a first insulating layer in contact with a sidewall of the cell active regions in the cell trench, and in contact with a sidewall of the peripheral active regions in the peripheral trench;
• forming a mask on the first insulating layer in the first region;
• forming a second insulating layer on the first insulating layer in the second region, using a selective dielectric-on-dielectric deposition process;
• after forming the second insulating layer, exposing the first insulating layer in the first region by removing the mask;
• forming a third insulating layer on the first insulating layer in the first region and on the second insulating layer in the second region;
• forming a fourth insulating layer on the third insulating layer;
• then
• performing a planarization process until an upper surface of the substrate is exposed;
• forming a gate trench crossing the cell active regions in the substrate in the first region;
• forming a gate in the gate trench;
• and
• forming a peripheral gate on the peripheral active regions in the second region.