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US 12,598,961 B2Granted
Semiconductor package including test pattern and method of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorYoungbae Kim
Life of this patent
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Abstract
Provided is a semiconductor package, including a first semiconductor chip, and a second semiconductor chip on the first semiconductor chip, wherein the first semiconductor chip includes a test pattern, and wherein a frequency based on stress being exerted on the first semiconductor chip is measured based on the test pattern.
Claims17
A semiconductor package, comprising:
- a first semiconductor chip having a rectangular shape;
- and
- a second semiconductor chip on the first semiconductor chip,
- wherein the first semiconductor chip comprises a plurality of test patterns,
- wherein each test pattern of the plurality of test patterns is configured to be used to measure a frequency based on stress exerted on the first semiconductor chip,
- wherein a width of the first semiconductor chip is greater than a width of the second semiconductor chip in a horizontal direction,
- wherein the plurality of test patterns comprise a first test pattern contacting a corner of the first semiconductor chip in which two sides of the rectangular shape of the first semiconductor chip intersect,
- wherein a second test pattern included in a region of an upper portion of the first semiconductor chip overlapping with an end portion of the second semiconductor chip in a vertical direction, and
- wherein a third test pattern included in a central region of the upper portion of the first semiconductor chip.
6 more elements
A semiconductor package, comprising:
- a first re-distribution layer;
- a first semiconductor chip on the first re-distribution layer, the first semiconductor chip comprising a plurality of test patterns;
- a second semiconductor chip on the first semiconductor chip, a width of the second semiconductor chip being smaller than a width of the first semiconductor chip in a horizontal direction;
- and
- a second re-distribution layer on the second semiconductor chip,
- wherein the first semiconductor chip is configured to measure a frequency based on stress being exerted on the first semiconductor chip.
3 more elements
A semiconductor package, comprising:
- a first re-distribution layer;
- a first semiconductor chip on the first re-distribution layer, the first semiconductor chip comprising a plurality of test patterns;
- a second semiconductor chip on the first semiconductor chip, a width of the second semiconductor chip being smaller than a width of the first semiconductor chip;
- a mold layer on the first semiconductor chip and the second semiconductor chip;
- a mold via penetrating the mold layer;
- and
- a second re-distribution layer on the mold layer,
- wherein each of the plurality of test patterns is configured to be used to measure a frequency that is caused by stress applied to the first semiconductor chip,
- wherein the first semiconductor chip further comprises a penetration via connected to each of the plurality of test patterns, and
- wherein the plurality of test patterns comprise a first test pattern adjacent to a corner of the first semiconductor chip, a second test pattern included in a region of an upper portion of the first semiconductor chip overlapping with an end portion of the second semiconductor chip in a vertical direction, and a third test pattern in a central region of the upper portion of the first semiconductor chip.
7 more elements
Dependencies are inferred from the claim text.