Method for analyzing layout pattern density

A method for analyzing a layout pattern density, comprising the following steps:

• step 1, providing layouts of a chip, repeatedly arrange the layouts, and merging the repeatedly arranged layouts to form a wafer level layout, wherein the wafer level layout presents a first circle in a top view, the size of the first circle is the same as the size of a second circle of a wafer used in a production line, the layout comprises a plurality of mask layers, and each mask layer comprises a plurality of patterns;
• step 2, segmenting the first circle to form a plurality of check windows;
• step 3, searching for the mask layer containing the patterns having a height morphology, and combining the found mask layers into a pattern layer combination;
• step 4, sequentially calculating a pattern density of the pattern layer combination in each check window;
• and
• step 5, recording the pattern density in each check window on a third circle to form a wafer level pattern density distribution diagram, wherein the size of the third circle is the same that of the first circle, and the position of each pattern density in the third circle is the same as the position of the check window corresponding to the pattern density in the first circle.