US 12,598,822 B2 · Stacked focal plane array circuit and method thereof

Abstract

A stacked focal planar array (FPA) device and method of fabrication. The method can include forming photodetectors or FPAs by heteroepitaxial growth of III-V PINs, APDs, or other photodetector devices that are bonded to a Si-based read-out integrated circuit (ROIC) wafer in a stacked configuration. In a single-color device example, a wavelength configuring buffer layer and photodetector are grown on a first substrate using compound semiconductor materials to enable infrared detection at desired wavelength(s). Depending on the application, this growth can be done on a graded compliant buffer layer and/or a selectively transparent buffer layer. And, silicon detectors can be incorporated to detect visible and NIR wavelengths in a dual-color device example. Further, the resulting devices can be bonded overlying the ROIC device in a flipped orientation and configured as pixels in a sensor array device coupled to the ROIC device.

A method of fabricating a stacked sensor device, the method comprising:

providing a partially completed semiconductor substrate comprising a semiconductor detector device formed overlying a first portion of a first substrate and a first dielectric layer formed overlying the semiconductor detector device and the first substrate;
forming a first cavity region within a portion of the first dielectric layer exposing a second portion of the first substrate;
forming a buffer material overlying the first substrate within the first cavity region, wherein forming the buffer material comprises a selective area heteroepitaxy process;
forming a plurality of photodetector device materials overlying the buffer material within the first cavity region to form a photodetector device overlying the first substrate, wherein forming the photodetector device comprises a selective area heteroepitaxy process;
forming a second dielectric layer overlying the first dielectric layer and the photodetector device;
forming a second cavity region within a portion of the first dielectric layer and the second dielectric layer exposing the semiconductor detector device;
subjecting the semiconductor detector device to one or more IC processing steps;
forming a dielectric material within the second cavity region overlying the semiconductor detector device;
forming a first metal interconnect within a portion of the second dielectric layer overlying the photodetector device, the first metal interconnect being coupled to the photodetector device;
forming a second metal interconnect within a portion of the first and second dielectric layers, the second metal interconnect being coupled to the semiconductor detector device;
forming a first bond pad overlying the second dielectric layer, the first bond pad being coupled to the first metal interconnect;
forming a second bond pad overlying the second dielectric layer, the second bond pad being coupled to the second metal interconnect;
wherein the partially completed semiconductor substrate, the photodetector device, the semiconductor detector device, the first dielectric layer, the second dielectric layer, the dielectric material, the first and second metal interconnects, and the first and second bond pads form a sensor device substrate;
providing a read-out integrated circuit (ROIC) substrate comprising a ROIC device overlying a second substrate and a third dielectric layer overlying the ROIC device and the second substrate, wherein the ROIC substrate includes a third metal interconnect and a fourth metal interconnect formed within the third dielectric layer and coupled to the ROIC device, and wherein the ROIC substrate includes a third bond pad and a fourth bond pad overlying the third dielectric layer such that the third bond pad is coupled to the third metal interconnect and the fourth bond pad is coupled to the fourth metal interconnect;
and
bonding the sensor device substrate overlying the ROIC substrate in a flipped orientation such that the first and second bond pads of the sensor device are coupled to the third and fourth bond pads of the ROIC substrate.

13 more elements

Stacked focal plane array circuit and method thereof

Life of this patent

Stacked focal plane array circuit and method thereof

Life of this patent

Abstract

Claims23