Vertical fin-based field effect transistor (FinFET) with connected fin tips

A vertical fin-based field effect transistor (FinFET) device comprising:

• an array of FinFETs comprising a plurality of rows and columns of fins, each of the fins having a fin length and a fin width measured laterally with respect to the fin length and including:
• a first fin tip disposed at a first end of each of the fins in a top view;
• a second fin tip disposed at a second end of each of the fins in the top view, wherein the second end opposes the first end;
• a central region disposed between the first fin tip and the second fin tip in the top view and characterized by an electrical conductivity;
• a bridging structure connecting the first fin tip to an adjacent fin in the top view, wherein the first fin tip laterally separates the bridging structure from the central region in the top view, and wherein the bridging structure comprises a neutralized structure characterized by a second electrical conductivity less than the electrical conductivity of the central region, and wherein the bridging structure is configured to reduce current leakage;
• and
• a source contact electrically coupled to the central region;
• a gate region surrounding each of the fins;
• a gate routing line;
• and
• a plurality of gate leads coupled to the gate routing line;
• wherein:
• at least one fin extends from a first row of the fins to a second row of the fins in the top view to reduce a number of fin tip ends in the array of FinFETs;
• the gate routing line is disposed between the first row of the fins and the second row of the fins in the top view;
• the plurality of gate leads each extend from the gate routing line between adjacent fins in the first row of the fins and adjacent fins in the second row of the fins towards each bridging structure in the top view;
• and
• the plurality of gate leads is configured to provide gate bias to the gate region surrounding each of the fins.