Integrated circuit structures having gate cut offset

An integrated circuit structure, comprising:

• a first fin;
• a second fin spaced apart from and parallel with the first fin;
• and
• a gate structure, comprising:
• a first gate structure portion over the first fin;
• a second gate structure portion over the second fin;
• and
• a gate cut between the first gate structure portion and the second gate structure portion, the gate cut laterally closer to the second fin than to the first fin, and the gate cut entirely outside of a footprint of the first fin and the second fin.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first vertical stack of horizontal nanowires;
• a second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires;
• and
• a gate structure, comprising:
• a first gate structure portion over the first vertical stack of horizontal nanowires;
• a second gate structure portion over the second vertical stack of horizontal nanowires;
• and
• a gate cut between the first gate structure portion and the second gate structure portion, the gate cut laterally closer to the second vertical stack of horizontal nanowires than to the first vertical stack of horizontal nanowires, and the gate cut entirely outside of a footprint of the first vertical stack of horizontal nanowires and the second vertical stack of horizontal nanowires.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first fin;
• a second fin spaced apart from and parallel with the first fin;
• and
• a gate structure, comprising:
• a first gate structure portion over the first fin;
• a second gate structure portion over the second fin;
• and
• a gate cut between the first gate structure portion and the second gate structure portion, the gate cut laterally closer to the second fin than to the first fin, and the gate cut entirely outside of a footprint of the first fin and the second fin.

An integrated circuit structure, comprising:

• a first vertical stack of horizontal nanowires;
• a second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires;
• and
• a gate structure, comprising:
• a first gate structure portion over the first vertical stack of horizontal nanowires;
• a second gate structure portion over the second vertical stack of horizontal nanowires;
• and
• a gate cut between the first gate structure portion and the second gate structure portion, the gate cut laterally closer to the second vertical stack of horizontal nanowires than to the first vertical stack of horizontal nanowires, wherein the gate cut is in a range of 10%-30% laterally closer to the second vertical stack of horizontal nanowires than to the first vertical stack of horizontal nanowires.