Gate spacers in semiconductor devices

A method, comprising:

• forming a stack of first and second nanostructured layers on a substrate;
• forming, on the stack of first and second nanostructured layers, a first gate spacer comprising a first dielectric constant;
• forming, on a sidewall of the first nanostructured layer, a second gate spacer comprising a second dielectric constant;
• removing the first nanostructured layer;
• forming a semiconductor layer on the second nanostructured layers;
• oxidizing the first gate spacer to form an oxygen-rich first gate spacer comprising a third dielectric constant lower than the first dielectric constant;
• and
• oxidizing the second gate spacer to form an oxygen-rich second gate spacer comprising a fourth dielectric constant lower than the second dielectric constant.

A semiconductor device, comprising:

• a substrate;
• a fin base disposed on the substrate;
• a source/drain (S/D) region disposed on the fin base;
• a nanostructured channel region disposed on the fin base;
• a gate structure surrounding the nanostructured channel region;
• an oxygen-rich outer gate spacer comprising:
• a first dielectric material with a first non-stoichiometric composition and disposed on a sidewall of the gate structure,
• a first region with a first silicon-to-nitrogen concentration ratio, and
• a second region with a second silicon-to-nitrogen concentration ratio different from the first silicon-to-nitrogen concentration ratio;
• and
• an oxygen-rich inner gate spacer comprising a second dielectric material with a second non-stoichiometric composition and disposed on an other sidewall of the gate structure.