Field effect transistor with dual layer isolation structure and method

A method, comprising:

• forming, between stacked first semiconductor nanostructures of a first transistor and second stacked semiconductor nanostructures of a second transistor, an isolation structure including:
• a core dielectric layer having a top surface higher than all of the first and second semiconductor nanostructures;
• and
• a shell dielectric layer surrounding a lower portion of the core dielectric layer and having a top surface lower than all of the first and second semiconductor nanostructures;
• and
• forming a high-K gate dielectric layer in contact with the sidewalls of the core dielectric layer;
• forming the shell dielectric layer on sidewalls of the first and second semiconductor nanostructures and having the top surface higher than all of the first and second semiconductor nanostructures;
• and
• etching the shell dielectric layer to remove shell dielectric layer from the sidewalls of the first and second semiconductor nanostructures and to recess the top surface of the shell dielectric layer to a level below all of the first and second semiconductor nanostructures;
• forming an interfacial dielectric layer in contact with the first and second semiconductor nanostructures, wherein forming the high-K gate dielectric layer includes depositing a first portion of the high-K gate dielectric on the interfacial dielectric layer and depositing a second portion of the high-K gate dielectric layer on the core dielectric layer where the shell dielectric layer was removed, wherein forming the high-K gate dielectric layer includes growing the high-K gate dielectric such that the first portion of the high-K gate dielectric merges with the second portion of the high-K gate dielectric.

A device, comprising:

• a semiconductor substrate;
• a first transistor including a plurality of stacked first semiconductor nanostructures over the substrate corresponding to channel regions of the first transistor;
• a second transistor including a plurality of stacked second semiconductor nanostructures over the substrate corresponding to channel regions of the second transistor;
• an isolation structure including:
• a core dielectric layer between the first semiconductor nanostructures and the second semiconductor nanostructures and having a top surface higher than all of the first and second semiconductor nanostructure;
• and
• a shell dielectric layer having:
• a primary portion surrounding a lower region of the core dielectric layer and having a top surface lower than all of the first and second semiconductor nanostructures;
• and
• a plurality of remnant portions each between the core dielectric layer and a respective one of the first and second semiconductor nanostructures.