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US 12,598,786 B2Granted
Field effect transistor structures
AssigneeAdeia Semiconductor Solutions LLC
InventorsJosephine B. Chang, Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
Life of this patent
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Abstract
Field effect transistors include a stack of nanowires of vertically arranged channel layers. A source and drain region is disposed at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Internal spacers are each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.
Claims21
A method of forming a semiconductor device, comprising:
- providing sacrificial layers and channel layers over a substrate, wherein the sacrificial layers alternate with the channel layers;
- etching through the sacrificial layers and the channel layers to form a fin;
- forming a first dummy gate over the fin;
- forming an adjacent second dummy gate over the fin while leaving an exposed region of the fin between the first dummy gate and the second dummy gate;
- etching through the sacrificial layers and the channel layers of the fin using the dummy gates as a mask to define an opening in the exposed region of the fin, wherein:
- the opening comprises a first sidewall and a second sidewall opposing the first sidewall;
- and
- the first and second sidewalls each comprise a plurality of exposed side surfaces of the channel layers and a plurality of exposed side surfaces of the sacrificial layers;
- and
- epitaxially growing source/drain material on the plurality of exposed side surfaces of the channel layers, wherein:
- the source/drain material grown on exposed side surfaces of first vertically adjacent channel layers comprised in the first sidewall merges to form a first source/drain region;
- the source/drain material grown on exposed side surfaces of second vertically adjacent channel layers comprised in the second sidewall merges to form a second source/drain region;
- and
- the first source/drain region does not merge with the second source/drain region.
11 more elements
A method of forming a semiconductor device, the method comprising:
- providing sacrificial layers and channel layers over a substrate, wherein the sacrificial layers alternate with the channel layers, wherein a lowermost layer of the sacrificial layers and the channel layers is a sacrificial layer, and wherein an uppermost layer of the sacrificial layers and the channel layers is a sacrificial layer;
- etching through the sacrificial layers and the channel layers to form a fin;
- forming a first dummy gate over the fin;
- forming an adjacent second dummy gate over the fin while leaving an exposed region of the fin between the first dummy gate and the second dummy gate;
- etching through the sacrificial layers and the channel layers of the fin using the dummy gates as a mask to define an opening in the exposed region of the fin, wherein:
- the opening comprises a first sidewall and a second sidewall opposing the first sidewall;
- and
- the first and second sidewalls each comprise a plurality of exposed side surfaces of the channel layers and a plurality of exposed side surfaces of the sacrificial layers;
- epitaxially growing source/drain material on the plurality of exposed side surfaces of the channel layers, wherein:
- the source/drain material grown on exposed side surfaces of first vertically adjacent channel layers comprised in the first sidewall merges to form a first source/drain region;
- and
- the source/drain material grown on exposed side surfaces of second vertically adjacent channel layers comprised in the second sidewall merges to form a second source/drain region;
- and
- filling a portion of the opening between the first source/drain region and the second source/drain region with a dielectric.
11 more elements
Dependencies are inferred from the claim text.