# US 12,598,780 B2 · Gate-all-around transistors with hybrid orientation

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- Number: US 12,598,780 B2
- Document ID: US12598780B2
- Status: Granted
- Kind: B2
- Application number: 17/807,945
- Filed: 2022-06-21
- Published: 2023-12-21
- Granted: 2026-04-07
- Earliest claimed: 2022-06-21
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Nicolas Jean Loubet; Shogo Mochizuki; Maruf Amin Bhuiyan
- Web page: https://patentgrep.com/patent/US12598780B2

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/364: {of IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes a p-type field-effect transistor including first channels made of silicon having a (110) crystallographic orientation. The semiconductor device further includes an n-type field-effect transistor including second channels made of silicon having a (100) crystallographic orientation. The semiconductor device further includes a gate surrounding the first channels and the second channels.

## Claims

### Claim 1

A semiconductor device, comprising:
a shared semiconductor substrate having a (110) crystallographic orientation;
a gate all around (GAA) p-type field-effect transistor including first channels made of silicon having a (110) crystallographic orientation;
a GAA n-type field-effect transistor including second channels made of silicon having a (100) crystallographic orientation;
a first gate surrounding the first channels;
a second gate surrounding the second channels;
a silicon oxide layer comprising a first bonding oxide layer directly connected to the shared semiconductor substrate and a second bonding oxide layer directly connected to a bottom surface of the second gate, wherein the first bonding oxide layer is directly connected to the second bonding oxide layer and wherein a bonding interface exists between the first bonding oxide layer and the second bonding oxide layer; and
a bottom dielectric isolation (BDI) layer directly connected to a bottom surface of the first gate and directly connected to the shared semiconductor substrate, wherein the BDI layer is composed of a different dielectric material than the silicon oxide layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein:
each of the first channels is a first silicon sheet;
each of the second channels is a second silicon sheet; and
the GAA p-type field-effect transistor includes a number of first silicon sheets that is equal to a number of second silicon sheets included in the GAA n-type field-effect transistor.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein:
a thickness of each of the first silicon sheets is substantially equal to a thickness of each of the second silicon sheets.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein:
each of the first silicon sheets is included in a p-type stack;
each of the second silicon sheets is included in an n-type stack; and
an uppermost surface of the p-type stack is substantially coplanar with an uppermost surface of the n-type stack.

### Claim 5

A semiconductor device, comprising:
a shared semiconductor substrate having a (100) crystallographic orientation;
a first gate all around (GAA) transistor over the shared semiconductor substrate, the first GAA transistor comprising first channels having a (100) crystallographic orientation;
a second GAA transistor over the shared semiconductor substrate, the second GAA transistor including second channels having a (110) crystallographic orientation;
a first gate surrounding the first channels;
a second gate surrounding the second channels;
a silicon oxide layer comprising a first bonding oxide layer directly connected to the shared semiconductor substrate and a second bonding oxide layer directly connected to a bottom surface of the second gate, wherein the first bonding oxide layer is directly connected to the second bonding oxide layer and wherein a bonding interface exists between the first bonding oxide layer and the second bonding oxide layer; and
a bottom dielectric isolation (BDI) layer directly connected to a bottom surface of the second gate and directly connected to the shared semiconductor substrate, wherein the BDI layer is composed of a different dielectric material than the silicon oxide layer.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein a number of first channels is equal to a number of second channels.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein a thickness of each of the first channels is substantially equal to a thickness of each of the second channels.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein an uppermost surface of a topmost first channel of the first channels is substantially coplanar with an uppermost surface of a topmost second channel of the second channels.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein a top surface of the silicon oxide layer is substantially coplanar with a top surface of the BDI layer.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein a bottom surface of the silicon oxide layer is substantially coplanar with a bottom surface of the BDI layer.

### Claim 11 (depends on 5)

The semiconductor device of claim 5, wherein a top surface of the silicon oxide layer is substantially coplanar with a top surface of the BDI layer.

### Claim 12 (depends on 5)

The semiconductor device of claim 5, wherein a bottom surface of the silicon oxide layer is substantially coplanar with a bottom surface of the BDI layer.