# US 12,598,779 B2 · Gate-all-around device with protective dielectric layer and method of forming the same

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- Number: US 12,598,779 B2
- Document ID: US12598779B2
- Status: Granted
- Kind: B2
- Application number: 18/623,285
- Filed: 2024-04-01
- Published: 2024-07-25
- Granted: 2026-04-07
- Earliest claimed: 2019-09-26
- Assignees: Taiwan Semiconductor Manufcaturing Co.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Cheng-Ting Chung; Yi-Bo Liao; Hou-Yu Chen; Kuan-Lun Cheng
- Web page: https://patentgrep.com/patent/US12598779B2

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/01: Manufacture or treatment
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 50/283: {by chemical means}
- H10P 50/642: {Chemical etching}
- H10P 50/73: {using masks for insulating materials}
- H10P 52/403: {of conductive or resistive materials}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/364: {of IGFETs}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.

## Claims

### Claim 1

A semiconductor structure comprising:
a semiconductor layer stack disposed over a substrate, wherein each semiconductor layer of the semiconductor layer stack extends lengthwise along a first direction;
a dielectric structure disposed over a topmost semiconductor layer of the semiconductor layer stack;
a gate stack disposed over the semiconductor layer stack, wherein the gate stack extends lengthwise along a second direction, the second direction is different than the first direction, and the gate stack includes a gate dielectric and a gate electrode; and
wherein:
in a first cross-sectional view of the semiconductor structure along the second direction, the gate stack at least wraps each semiconductor layer of the semiconductor layer stack, and the gate stack wraps the dielectric structure, and
in a second cross-sectional view of the semiconductor structure along the first direction, a first gate stack portion of the gate stack is disposed between the dielectric structure and a top of the topmost semiconductor layer of the semiconductor layer stack, and a second gate stack portion of the gate stack is disposed between a bottom of the topmost semiconductor layer of the semiconductor layer stack and a top of another semiconductor layer of the semiconductor layer stack.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein each semiconductor layer of the semiconductor layer stack has a first width along the second direction, the dielectric structure has a second width along the second direction, and the first width is equal to the second width.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein each semiconductor layer of the semiconductor layer stack has a first length along the first direction, the dielectric structure has a second length along the first direction, and the first length is equal to the second length.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein each semiconductor layer of the semiconductor layer stack has a first thickness along a third direction that is different than the first direction and the second direction, the dielectric structure has a second thickness along the third direction, and the first thickness is less than the second thickness.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the first gate stack portion of the gate stack has a first thickness along a third direction that is different than the first direction and the second direction, the second gate stack portion of the gate stack has a second thickness along the third direction, and the first thickness is equal to the second thickness.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein a first distance is between the dielectric structure and the top of the top semiconductor layer of the semiconductor layer stack, a second distance is between the bottom of the top semiconductor layer of the semiconductor layer stack and the top of the another semiconductor layer of the semiconductor layer stack, the first distance and the second distance are each along a third direction that is different than the first direction and the second direction, and the first distance is equal to the second distance.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, further comprising:
first inner spacers;
second inner spacers;
gate spacers; and
wherein:
in the second cross-sectional view of the semiconductor structure along the first direction, the first inner spacers are disposed along sidewalls of the first gate stack portion of the gate stack, the first inner spacers are disposed between the dielectric structure and the top semiconductor layer, and the first inner spacers abut the dielectric structure and the top semiconductor layer,
in the second cross-sectional view of the semiconductor structure along the first direction, the second inner spacers are disposed along sidewalls of the second gate stack portion of the gate stack, the second inner spacers are disposed between the top semiconductor layer and the another semiconductor layer, and the second inner spacers abut the top semiconductor layer and the another semiconductor layer, and
in a third cross-sectional view of the semiconductor structure along the first direction, the gate spacers are disposed along sidewalls of the gate stack.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a contact etch stop layer (CESL);
an interlayer dielectric (ILD) layer disposed over the CESL;
a self-aligned contact (SAC) dielectric structure; and
wherein:
in the second cross-sectional view of the semiconductor structure along the first direction, the CESL is disposed along sidewalls of the dielectric structure and the CESL is between the dielectric structure and the ILD layer, and
in the first cross-sectional view of the semiconductor structure along the second direction, the SAC dielectric structure is disposed along sidewalls of the dielectric structure and the gate dielectric of the gate stack is between the dielectric structure and the SAC dielectric structure.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric structure is formed of a dielectric material that includes metal and oxygen.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric structure is formed of a dielectric material that includes silicon and nitrogen, carbon, or both.

### Claim 11

A semiconductor structure comprising:
a material layer stack disposed over a semiconductor protrusion, wherein the semiconductor protrusion is disposed over and abuts a substrate, the material layer stack includes a dielectric layer disposed over a semiconductor layer, and the semiconductor layer is disposed over the semiconductor protrusion;
an isolation structure disposed over and abutting the substrate, wherein the isolation structure is disposed along and abuts sidewalls of the semiconductor protrusion; and
a gate stack having a first portion disposed on the isolation structure and a second portion disposed on the material layer stack and the semiconductor protrusion, wherein:
the gate stack includes a gate dielectric and a gate electrode,
the gate stack abuts and wraps the dielectric layer, abuts and surrounds the semiconductor layer, and abuts the isolation structure,
the second portion is disposed between inner spacers along a widthwise direction of the gate stack, and
the first portion is disposed between gate spacers along the widthwise direction of the gate stack.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein a first sub-portion of the first portion of the gate stack abuts a top of the semiconductor layer and the dielectric layer, a second sub-portion of the first portion of the gate stack abuts a bottom of the semiconductor layer, and the first sub-portion and the second portion have a same height.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein:
the semiconductor layer is a first semiconductor layer, the material layer stack includes a second semiconductor layer disposed between the first semiconductor layer and the semiconductor protrusion, the first portion abuts the second semiconductor layer, and the first portion surrounds the second semiconductor layer; and
the first sub-portion is disposed between the dielectric layer and the top of the first semiconductor layer and the second sub-portion is disposed between the bottom of the first semiconductor layer and a top of the second semiconductor layer.

### Claim 14 (depends on 13)

The semiconductor structure of claim 13, wherein:
the inner spacers include first inner spacers and second inner spacers;
the first inner spacers are disposed along sidewalls of the first sub-portion; and
the second inner spacers are disposed along sidewalls of the second sub-portion.

### Claim 15 (depends on 11)

The semiconductor structure of claim 11, wherein the dielectric layer is a first metal oxide layer, and the gate dielectric is a second metal oxide layer.

### Claim 16 (depends on 11)

The semiconductor structure of claim 11, wherein the gate spacers abut the dielectric layer of the material layer stack.

### Claim 17

A device comprising:
a first source/drain and a second source/drain disposed over a substrate;
a channel layer disposed over the substrate, wherein the channel layer extends along from the first source/drain to the second source/drain;
a gate stack that is disposed on a top, a bottom, and a sidewall of the channel layer, wherein that gate stack includes a gate dielectric and a gate electrode, the gate stack includes a first gate stack portion and a second gate stack portion, the first gate stack portion extends along a gate height direction from a bottom of a gate hard mask to the top of the channel layer, the second gate stack portion extends along the gate height direction from the bottom of the channel layer towards the substrate, the first gate stack portion abuts the bottom of the gate hard mask and the top of the channel layer, and the second gate stack portion abuts the bottom of the channel layer;
first dielectric spacers disposed along sidewalls of the first gate stack portion, wherein the first dielectric spacers extend along the gate height direction from the gate hard mask to the top of the channel layer, and further wherein the first dielectric spacers abut the gate hard mask, the top of the channel layer, the first source/drain, and the second source/drain; and
second dielectric spacers disposed along sidewalls of the second gate stack portion, wherein the second dielectric spacers extend along the gate height direction from the bottom of the channel layer towards the substrate, and further wherein the second dielectric spacers abut the bottom of the channel layer, the first source/drain, and the second source/drain.

### Claim 18 (depends on 17)

The device of claim 17, wherein a first height of the first dielectric spacers is equal to a second height of the second dielectric spacers, wherein the first height and the second height are along the gate height direction.

### Claim 19 (depends on 17)

The device of claim 17, wherein a first height of the first gate stack portion is equal to a second height of the second gate stack portion, wherein the first height and the second height are along the gate height direction.

### Claim 20 (depends on 17)

The device of claim 17, wherein first lateral dimensions of the gate hard mask are equal to second lateral dimensions of the channel layer.