Nanosheet epitaxy with full bottom isolation

A semiconductor device comprising:

• a first set of semiconductor channel layers vertically aligned and stacked one on top of another;
• a heavily doped p-type field effect transistor (p-FET) source drain epitaxy region adjacent to the first set of semiconductor channel layers, wherein a horizontal lower surface of the p-FET source drain epitaxy region is adjacent to a horizontal upper surface of an undoped silicon epitaxy;
• a heavily doped n-type field effect transistor (n-FET) source drain epitaxy doped region adjacent to a second set of semiconductor channel layers, wherein a horizontal lower surface of the n-FET source drain epitaxy region is adjacent to the horizontal upper surface of the undoped silicon epitaxy;
• a bottom isolation region aligned below the undoped silicon epitaxy and below the semiconductor channel layers;
• and
• a seed layer separating the bottom isolation and undoped silicon epitaxy.

A method comprising:

• forming a first stack of nanosheet layers on a substrate, a second stack of nanosheet layers on the substrate, and a third stack of nanosheet layers on the substrate, the first stack, the second stack and the third stack of nanosheet layers each comprising alternating layers of a sacrificial and a semiconductor channel vertically aligned and stacked one on top of another;
• forming a first sacrificial gate across the first stack of nanosheet layers, a second sacrificial gate across the second stack of nanosheet layers and a third sacrificial gate across the third stack of nanosheet layers;
• and
• forming an undoped silicon epitaxy between the first stack and the second stack of nanosheet layers and between the second stack and the third stack of nanosheet layers.