Source/drains in semiconductor devices and methods of forming thereof

A method comprising:

• providing a silicon on insulator (SOI) substrate, the SOI substrate comprising a top semiconductor layer over an insulator layer;
• performing a first etch process in a first processing chamber to form a source/drain recess in the top semiconductor layer, wherein after performing the first etch process, a bottom surface of the source/drain recess extends below a top surface of the top semiconductor layer by a first distance;
• and
• after performing the first etch process, performing a second etch process in a second processing chamber to further extend the source/drain recess into the top semiconductor layer, wherein after performing the second etch process, a bottom surface of the source/drain recess extends below the top surface of the top semiconductor layer by a second distance, wherein the second distance is greater than the first distance, wherein the first etch process is different from the second etch process, and wherein the second processing chamber is different from the first processing chamber, wherein the second etch process is a fluorine-ozone mixture (FOM) process, wherein the FOM process is a cyclical process, and wherein the FOM process comprises:
• exposing portions of the top semiconductor layer in the source/drain recess to ozone to form an oxide region in the source/drain recess;
• and
• removing the oxide region using diluted hydrogen fluoride (dHF) as an etchant;
• growing a source/drain region in the source/drain recess;
• and
• forming a gate structure on a top surface of the SOI substrate and adjacent to the source/drain region.

A method comprising:

• forming a gate stack on a silicon on insulator (SOI) substrate, the SOI substrate comprising:
• a base semiconductor layer;
• an insulator layer over the base semiconductor layer;
• and
• a top semiconductor layer over the insulator layer;
• depositing a gate spacer layer over top surfaces and sidewalls of the gate stack, and over top surfaces of the top semiconductor layer;
• performing a first etch process to etch portions of the gate spacer layer and define gate spacers on the sidewalls of the gate stacks;
• performing a second etch process to form a recess in the top semiconductor layer;
• and
• performing a third etch process to extend the recess further into the top semiconductor layer, wherein the first etch process, the second etch process, and the third etch process are different from each other, and wherein the third etch process comprises:
• forming an oxide region in the top semiconductor layer, the oxide region being disposed on sidewalls and a bottom surface of the recess, wherein forming the oxide region comprises exposing top surfaces and sidewalls of the top semiconductor layer to a process gas comprising ozone;
• and
• removing the oxide region.