Vertical trench gate fet with split gate

A semiconductor device, comprising:

• a drift region having a first surface;
• first and second source regions, and a plurality of third source regions, located over the drift region and being electrically connected to a source terminal;
• a first body structure between the first source region and the drift region;
• a second body structure between the second source region and the drift region;
• a plurality of third body structures each located between a corresponding one of the third source regions and the drift region;
• and
• a first gate corresponding to the first body structure, a second gate corresponding to the second body structure, and a plurality of third gates each corresponding to one of the third body structures, each third gate directly neighboring at least one other third gate, wherein the first gate and the second gate are conductively connected to a first gate signal node configured to receive a first voltage, the first, second and third gates being noncontiguous with respect to each other, and having short axes in a first direction and long axes in a second direction, the short axes being colinear along the first direction;
• and
• the third gates are conductively connected to a second gate signal node configured to receive a second voltage.

A method of forming a semiconductor device, comprising:

• forming a first trench, a second trench, and a plurality of third trenches in a semiconductor layer of a first conductivity type, each of the trenches being noncontiguous with respect to each other;
• forming corresponding oxide layers over inner walls of the first, second and third trenches;
• forming a first polysilicon plate in the first trench, a second polysilicon plate in the second trench, and corresponding third polysilicon plates in the third trenches;
• forming a first gate over the first polysilicon plate, a second gate over the second polysilicon plate and corresponding third gates over the third polysilicon plates;
• forming first and second body structures of a second conductivity type over the semiconductor layer, the first body structure extending from the first trench to a first one of the third trenches and the second body structure extending from the second trench to a second one of the third trenches;
• forming a third body structure extending from a first one of the third trenches to a second one of the third trenches;
• forming a first source region of the first conductivity type over the first body structure, a second source region of the first conductivity type over the second body structure and corresponding third source regions of the first conductivity type over the third body structures;
• conductively connecting the first and second gates to a first gate signal node;
• and
• conductively connecting the third gates to a second gate signal node conductively isolated from the first gate signal node.

An integrated circuit, comprising:

• a plurality of trenches formed in a semiconductor substrate having a first conductivity type, including a first trench, a second trench and a plurality of third trenches between the first and second trenches, each of the trenches being noncontiguous with respect to each other;
• a first field plate within the first trench, a second field plate within the second trench and third field plates within the third trenches;
• a first gate structure over the first field plate, a second gate structure over the second field plate and third gate structures over the third field plates;
• a first source region extending from the first trench to a first one of the third trenches, a second source region extending from the second trench to a second one of the third trenches, and a third source region extending from two adjacent ones of the third trenches;
• a source node connected to the first, second and third source regions;
• a first gate node connected to the first and second gate structures;
• and
• a second gate node connected to the two adjacent ones of the third gate structures and conductively isolated from the first and third gate structures.