Semiconductor device structure with metal gate stack

A semiconductor device structure, comprising:

• a plurality of first semiconductor nanostructures over a first semiconductor fin;
• a plurality of second semiconductor nanostructures stacked in a first direction over a second semiconductor fin, wherein a topmost second semiconductor nanostructure of the second semiconductor nanostructures is thinner than each of lower semiconductor nanostructures of the second semiconductor nanostructures in the first direction, and the second semiconductor fin is thicker than the topmost second semiconductor nanostructure;
• a first epitaxial structure and a second epitaxial structure, wherein the second semiconductor nanostructures are sandwiched between the first epitaxial structure and the second epitaxial structure, and a bottommost surface of the first epitaxial structure is positioned vertically below a topmost surface of the second semiconductor fin and above a bottommost surface of the second semiconductor fin;
• a first conductive contact electrically connected to the first epitaxial structure;
• a second conductive contact electrically connected to the second epitaxial structure;
• a conductive feature extending across the first conductive contact and the second conductive contact, wherein the second conductive contact is electrically connected to the first conductive contact through the conductive feature;
• a first metal gate stack wrapped around the first semiconductor nanostructures;
• and
• a second metal gate stack wrapped around the second semiconductor nanostructures.

A semiconductor device structure, comprising:

• a plurality of first semiconductor nanostructures over a first semiconductor fin;
• a plurality of second semiconductor nanostructures stacked in a first direction over a second semiconductor fin, wherein a topmost second semiconductor nanostructure of the second semiconductor nanostructures and one of lower semiconductor nanostructures of the second semiconductor nanostructures have different thicknesses in the first direction, and the second semiconductor fin is thicker than the topmost second semiconductor nanostructure;
• a first metal gate stack wrapped around the first semiconductor nanostructures;
• a second metal gate stack wrapped around the second semiconductor nanostructures;
• a first epitaxial structure and a second epitaxial structure, wherein the second semiconductor nanostructures are sandwiched between the first epitaxial structure and the second epitaxial structure;
• a first conductive contact electrically connected to the first epitaxial structure;
• a second conductive contact electrically connected to the second epitaxial structure;
• a conductive feature extending across the second metal gate stack, wherein the second conductive contact is electrically connected to the first conductive contact through the conductive feature;
• and
• an isolation structure laterally surrounding a lower portion of the second semiconductor fin, wherein the second semiconductor fin protrudes from a top surface of the isolation structure.