Methods of manufacturing a semiconductor device with local isolation and a semiconductor device with local isolation

A method of manufacturing a semiconductor device, comprising:

• forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;
• forming a sacrificial gate structure over the fin structure;
• etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;
• forming cavities on an end of each of the first semiconductor layers where the first semiconductor layers intersect with the source/drain space by laterally etching the first semiconductor layers through the source/drain space;
• forming an inner spacer made of a dielectric material in the cavities of the first semiconductor layers;
• forming an electrical isolation region at a bottom of the source/drain region, wherein the electrical isolation region produces an electrical barrier, the electrical isolation region includes a void region, and an interface between a lowest first semiconductor layer and a lowest second semiconductor layer is aligned with a bottom surface of the void region;
• and
• forming a doped source/drain epitaxial layer over the electrical isolation region in the source/drain space.

A method of manufacturing a semiconductor device, comprising:

• forming a fin structure over a substrate, wherein the fin structure includes channel semiconductor layers and sacrificial semiconductor layers alternately stacked;
• forming a sacrificial gate structure over the fin structure;
• etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;
• forming an isolation region at a bottom portion of the source/drain space;
• and
• forming a source/drain epitaxial layer over the isolation region in the source/drain space, wherein the isolation region includes a dielectric region, an insulating layer in the isolation region, and a void region between the source/drain epitaxial layer and the insulating layer and between the source/drain epitaxial layer and the dielectric region.