Electronic device having stacked structures and method for manufacturing the same

An electronic device comprising:

• a first conductive layer;
• a second conductive layer connected to the first conductive layer;
• a stacked structure including conductive layers and insulating layers which are alternately stacked over the second conductive layer;
• a channel layer passing through the stacked structure and including a contact surface connected to the second conductive layer;
• and
• a memory layer between the channel layer and the stacked structure,
• wherein the conductive layers include a selection gate of a selection transistor and gate electrodes of memory cells, and
• wherein the selection gate is located between the first conductive layer and the gate electrodes.

An electronic device comprising:

• a first conductive layer;
• a second conductive layer connected to the first conductive layer;
• a stacked structure including conductive layers and insulating layers which are alternately stacked over the second conductive layer;
• a channel layer passing through the stacked structure and including a contact surface connected to the second conductive layer;
• a memory layer between the channel layer and the stacked structure;
• and
• a slit insulating layer passing through the insulating layers of the stacked structure,
• wherein the slit insulating layer includes protrusions located between the insulating layers and located on sidewalls of the conductive layers.

An electronic device comprising:

• a first conductive layer;
• a second conductive layer connected to the first conductive layer;
• a stacked structure including conductive layers and insulating layers which are alternately stacked over the second conductive layer;
• a channel layer passing through the stacked structure and including a contact surface connected to the second conductive layer;
• and
• a memory layer between the channel layer and the stacked structure,
• wherein the stacked structure includes a first structure and a second structure over the first structure,
• wherein the conductive layers includes first and second gate electrodes of memory cells,
• wherein the first structure includes the first gate electrodes spaced apart from each other at a first interval,
• wherein the second structure includes the second gate electrodes spaced apart from each other at a second interval, and
• wherein one first gate electrode and one second gate electrode adjacent to each other, among the first and second gate electrodes, are spaced apart from each other at a third interval greater than each of the first interval and the second interval.