Memory cell, nonvolatile semiconductor storage device, and method for manufacturing nonvolatile semiconductor storage device

A memory cell comprising:

• a semiconductor substrate covered by an insulating layer;
• a fin disposed on the insulating layer;
• a memory gate structure including a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a memory gate electrode stacked, and being disposed on the insulating layer so as to extend over the fin;
• a first sidewall spacer disposed on one sidewall of the memory gate structure;
• a second sidewall spacer disposed on another sidewall of the memory gate structure;
• a first select gate structure including a first select gate electrode stacked on a first select gate insulating film, and being disposed on the insulating layer so as to extend over the fin along the first sidewall spacer;
• a second select gate structure including a second select gate electrode stacked on a second select gate insulating film, and being disposed on the insulating layer so as to extend over the fin along the second sidewall spacer;
• a drain region provided adjacent to the first select gate structure on a surface of the fin, insulated from the first select gate electrode, and electrically connected with a bit line;
• and
• a source region provided adjacent to the second select gate structure on the surface of the fin, insulated from the second select gate electrode, and electrically connected with a source line, wherein:
• the first select gate structure, the memory gate structure, and the second select gate structure are provided between the drain region and the source region,
• an upper insulating layer is provided on an upper surface of the fin in a region where the memory gate structure, the first sidewall spacer, the first select gate structure, the second sidewall spacer, and the second select gate structure are provided,
• a first select gate sidewall insulating film is provided between the first select gate electrode and the first sidewall spacer, the first select gate sidewall insulating film being formed along the first sidewall spacer and being integrally formed with the first select gate insulating film,
• a second select gate sidewall insulating film is provided between the second select gate electrode and the second sidewall spacer, the second select gate sidewall insulating film being formed along the second sidewall spacer and being integrally formed with the second select gate insulating film, and
• the insulating layer includes:
• a layered insulating layer provided on the semiconductor substrate;
• and
• a lower insulating layer that is provided on the layered insulating layer, made of a material same as a material of the layered insulating layer, and integrated with the layered insulating layer, and on a surface of which the fin is provided,
• the layered insulating layer, the lower insulating layer, the fin, and the upper insulating layer are stacked in this order on the semiconductor substrate, and
• the layered insulating layer is wider than the lower insulating layer, the width being a direction orthogonal to a longitudinal direction in which the fin extends and orthogonal to a stacking direction of the layered insulating layer, the lower insulating layer, the fin, and the upper insulating layer.