US 12,598,739 B2Granted

Semiconductor device

AssigneeSamsung Electronics Co., Ltd.

InventorsJihoon Chang, Dong-Wan Kim, Dong-Sik Park

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Abstract

A semiconductor device includes a substrate having an active cell region and an interfacial region adjacent to each other in a first direction, bit lines on the active cell region of the substrate that are spaced apart from each other in a second direction that intersects the first direction, and bit-line pads on the interfacial region of the substrate that are spaced apart from each other in the second direction. Each of the bit lines includes a first bit line and a second bit line that extend in the first direction and are spaced apart from each other in the second direction, a connection part that connects a first end of the first bit line to a second end of the second bit line, and a coupling part that connects one of the bit-line pads to one of the first bit line, the second bit line, and the connection part.

Claims19

Dependent claims

A semiconductor device, comprising:

a substrate including an active cell region and an interfacial region, the active cell region and the interfacial region being adjacent to each other in a first direction;
bit lines on the active cell region of the substrate, the bit lines being spaced apart from each other in a second direction that intersects the first direction;
and
bit-line pads on the interfacial region of the substrate, the bit-line pads being spaced apart from each other in the second direction,
wherein each of the bit lines includes:
a first bit line and a second bit line that extend in the first direction, the first bit line and the second bit line being spaced apart from each other in the second direction;
a connection part that connects a first end of the first bit line to a second end of the second bit line;
and
a coupling part that connects one of the bit-line pads to one of the first bit line, the second bit line, and the connection part, and
wherein the first bit line, the second bit line, the connection part, and the coupling part are a single unitary piece.

7 more elements

A semiconductor device, comprising:

a substrate including active cell regions and interfacial regions between the active cell regions, the active cell regions being arranged in a first direction;
bit lines on the active cell regions of the substrate, the bit lines extending in the first direction and being spaced apart from each other in a second direction that intersects the first direction;
and
bit-line pads on the interfacial regions of the substrate, the bit-line pads being spaced apart from each other in the second direction,
wherein the active cell regions include:
outermost active cell regions on opposite sides in the first direction;
and
central active cell regions between the outermost active cell regions, the central active cell regions being adjacent to each other in the first direction,
wherein the bit lines include:
first bit lines and second bit lines that are alternately arranged along the second direction on the outermost active cell regions;
and
third bit lines and fourth bit lines that are alternately arranged along the second direction on the central active cell regions,
wherein a pair of neighboring ones of the first bit lines and the second bit lines are connected to each other through a connection part, the connection part extending between the pair of neighboring ones of the first bit lines and the second bit lines, and
wherein the third bit lines and the fourth bit lines are connected to different ones of the bit-line pads.

11 more elements

A semiconductor device, comprising:

a substrate including an active cell region and an interfacial region, the active cell region and the interfacial region being adjacent to each other in a first direction;
word lines on the active cell region of the substrate, the word lines extending in a second direction that intersects the first direction and being spaced apart from each other in the first direction;
bit lines on the active cell region of the substrate, the bit lines extending in the first direction and being spaced apart from each other in the second direction;
and
bit-line pads on the interfacial region of the substrate and spaced apart from each other in the second direction,
wherein, when viewed in a plan view, each of the bit lines has a U shape, each of the word lines twice crossing each of the bit lines, and
wherein each of the bit lines is connected to one of the bit-line pads.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/854,130Filed 30 Jun 2022
Priority: KR 10-2021-018007415 Dec 2021
Published: US 2023/0189510 A115 Jun 2023
Granted: 7 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10B 12/09
Manufacture or treatment: with simultaneous manufacture of the peripheral circuit region and memory cells
H10B 12/50
Dynamic random access memory [DRAM] devices: peripheral circuit region structures
G11C 5/025
Disposition of storage elements, e.g. in the form of a matrix array: geometric lay-out considerations of storage- and peripheral-blocks in a…
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out