Method of making 3D memory stacking formation with high circuit density

A semiconductor device, comprising:

• a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate, wherein at least one DRAM cell unit comprises a transistor and a capacitor,
• wherein the capacitor comprises:
• a first metal laver,
• a capacitor dielectric layer positioned on the first metal layer, and
• a second metal layer positioned on the capacitor dielectric layer,
• wherein the capacitor is elongated in a horizontal direction parallel to the working surface of the substrate, and the second metal layer has a first end and a second end in the horizontal direction,
• wherein the transistor comprises:
• a channel structure, and
• a gate structure disposed all around the channel structure,
• wherein the first metal layer extends in the horizontal direction beyond the first end of the second metal layer to form a drain region and a source region of the transistor,
• the capacitor dielectric layer is at least partially at a higher level in the vertical direction than the channel structure,
• the second metal layer is at least partially at a higher level in the vertical direction than the channel structure, and
• a capacitor metal portion of the first metal layer, which is in direct contact with the capacitor dielectric layer, is wider than the drain region and the source region in another horizontal direction.

A method of manufacturing a semiconductor device, the method comprising:

• forming a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate, wherein at least one DRAM cell unit comprises a transistor and a capacitor, and the forming the stack of DRAM cell units comprises forming the transistor and forming the capacitor,
• wherein the forming the capacitor comprises:
• forming a first metal laver,
• forming a capacitor dielectric layer positioned on the first metal layer, and
• forming a second metal layer positioned on the capacitor dielectric layer,
• wherein the capacitor is elongated in a horizontal direction parallel to the working surface of the substrate, and the second metal layer has a first end and a second end in the horizontal direction,
• wherein the forming the transistor comprises:
• forming a channel structure, and
• forming a gate structure disposed all around the channel structure,
• wherein the first metal layer extends in the horizontal direction beyond the first end of the second metal layer to form a drain region and a source region of the transistor,
• the capacitor dielectric layer is at least partially at a higher level in the vertical direction than the channel structure,
• the second metal layer is at least partially at a higher level in the vertical direction than the channel structure,
• the first metal layer is coplanar with the channel structure, and
• the drain region and the source region of the first metal layer are in direct contact with the channel structure.