Top-down relative DAC calibration

A method for calibrating a digital-to-analog converter device (DAC), the DAC having plural DAC segments generating an output voltage signal responsive to activated input bits, said method comprising:

• receiving, at a first input of a comparator device, in an iterative fashion, a first output voltage from a DAC under calibration in a first iteration and a second output voltage from the DAC under calibration in a second subsequent iteration, the first output voltage corresponding to a summation of outputs provided by a first subset of one or more DAC segments of the DAC being calibrated, and the second output voltage corresponding to a summation of outputs provided by a second subset of one or more DAC segments of the DAC being calibrated, the first subset of DAC segments being of a strength nominally equal to that of the second subset of DAC segments;
• receiving at a voltage DAC (VDAC) circuit, at the first iteration, an input digital word that is tuned to generate a reference output voltage substantially equal to the first output voltage, wherein at the first iteration, the comparator device receives at a second input, the generated reference output voltage and compares the first output voltage with the reference output voltage, and tuning said digital word until an output signal of the comparator device indicates that the reference output voltage generated by said VDAC is substantially equal to the first output voltage;
• receiving at the second input of the comparator device, at the second iteration, the reference output voltage generated at the first iteration and comparing, by the comparator device at the second iteration, the received second output voltage with the reference output voltage, the comparator device providing an output signal based on a difference between the second output voltage and the reference output voltage;
• and
• receiving, at a control logic circuit, said comparator device output signal, and
• generating, at the control logic circuit, in response to said comparator device output signal, one or more calibration signals for input to the DAC under calibration to tune the second subset of one or more DAC segments of the DAC being calibrated such that a strength of a summation of outputs provided by the second subset of one or more DAC segments substantially equals the reference output voltage, and
• iteratively tuning, by the control logic circuit, using said one or more calibration signals, each of the relative strengths of DAC segment outputs of successive second subsets of DAC segments to match each of corresponding successive first subsets of DAC segments, the subsequent first subsets of DAC segments being of strengths nominally equal to those of the subsequent second subsets of DAC segments.