Delay calibration circuit and method, analog-to-digital converter, radar sensor, and device
AssigneeCalterah Semiconductor Technology (Shanghai) Co., Ltd.
InventorsXinlong Zhang, Wenting Zhou
Life of this patent
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Abstract
A delay calibration circuit and method, an analog-to-digital converter, a radar sensor, and a device are provided. The delay calibration circuit monitors a timing relationship between signals in a chip in real time to extract PVT information, dynamically adjusts conversion timing of an asynchronous SAR ADC, maximally utilizes an available conversion time in each cycle of the asynchronous SAR ADC, improves the robustness of the asynchronous SAR ADC, and does not affect the normal operation of the asynchronous SAR ADC.
Claims20
A delay calibration circuit, arranged within a successive approximation register (SAR) analog-to-digital converter (ADC), wherein the SAR ADC is configured to convert an analog signal sampled in a present sampling cycle into a digital signal of N bits, N>1;
- wherein the delay calibration circuit comprises:
- a monitoring circuit, configured to monitor a completion time of the analog signal being converted in the present sampling cycle and to output a detection signal in response to a last bit of the N bits having been generated in the present sampling cycle;
- and
- an adjustable delay calibration circuit coupled with the monitoring circuit and configured to adjust at least one delay duration according to timing information between the detection signal and a sampling clock signal of a next sampling cycle, wherein each delay duration of the at least one delay duration corresponds to a respective length of time spent by the SAR ADC to generate a respective bit of the N bits in the next sampling cycle;
- wherein the adjustable delay calibration circuit comprises:
- a plurality of adjustable delay modules, wherein the each delay duration for the respective bit is adjusted using at least one respective adjustable delay module of the plurality of adjustable delay modules;
- and
- a digital calibration circuit coupled with each adjustable delay module of the plurality of adjustable delay modules and the monitoring circuit, and configured to receive the detection signal and the sampling clock signal, to generate an M-bit digital control code for the respective bit of the N bits according to the timing information, and to output the M-bit digital control code to the at least one respective adjustable delay module, and wherein M is greater than or equal to 1 and is equal to a number of the at least one respective adjustable delay module.
A delay calibration method, comprising:
- monitoring a completion time of an analog signal sampled in a present sampling cycle and being converted into a digital signal of N bits, wherein N>1;
- outputting a detection signal in response to a last bit of the N bits having been generated in the present sampling cycle;
- and
- adjusting at least one delay duration according to timing information between the detection signal and a sampling clock signal of a next sampling cycle, wherein each delay duration of the at least one delay duration corresponds to a respective length of time spent by the SAR analog-to-digital converter (ADC) to generate a respective bit of the N bits in the next sampling cycle;
- wherein adjusting the at least one delay duration according to the timing information between the detection signal and the sampling clock signal of the next sampling cycle, comprises:
- generating an M-bit digital control code for the respective bit of the N bits in the next sampling cycle according to a detection result of the timing information;
- outputting the M-bit digital control code to at least one corresponding adjustable delay module of a plurality of adjustable delay modules, wherein the at least one corresponding adjustable delay module is configured to adjust a delay duration of the at least one delay duration for the respective bit of the N bits;
- and
- adjusting the delay duration of the at least one delay duration using the at least one corresponding adjustable delay module and the M-bit digital control code, wherein M is greater than or equal to 1 and is equal to a number of the at least one respective adjustable delay module.
Dependencies are inferred from the claim text.