Reduce DCO frequency overlap-induced limit cycle in hybrid and digital PLLS

A clock tracking circuit comprising:

• a phase locked loop (PLL) to generate an output signal from a reference signal in response to a digital phase error signal and generate digital control oscillator (DCO) codes;
• a DCO included in the PLL to generate the output signal based on a value of a DCO code;
• a circuit to generate an adjustment signal based on the DCO codes for changing a current value of the DCO code to a new value responsive to determining that a value of the DCO code being associated with a boundary of a DCO frequency overlap region;
• and
• a controller coupled to the DCO to receive a control signal and generate the output signal, wherein the controller, for reducing effects of frequency redundancy, to:
• observe that a DCO frequency is at the boundary of the DCO frequency overlap region by observing the DCO code to determine when a DCO code being utilized to set a DCO frequency matches a DCO code value associated with a boundary of a DCO frequency overlap region having a corresponding value or a corresponding range of values of the DCO code, and
• bypass at least a portion of the DCO frequency overlap region by bypassing one or more DCO code values associated with a portion of the DCO frequency overlap region by jumping at least some of the one or more DCO code values.